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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
commit | 52355f5185fe42e28775e897f458b38a439c0ec5 (patch) | |
tree | 83d8984e70806c9bcc8cd6d72ea81456ca76aba6 /passes/opt/opt_muxtree.cc | |
parent | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (diff) | |
download | yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.gz yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.bz2 yosys-52355f5185fe42e28775e897f458b38a439c0ec5.zip |
Use more ID::{A,B,Y,blackbox,whitebox}
Diffstat (limited to 'passes/opt/opt_muxtree.cc')
-rw-r--r-- | passes/opt/opt_muxtree.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 61f194569..3d7e9cccb 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -86,10 +86,10 @@ struct OptMuxtreeWorker { if (cell->type.in(ID($mux), ID($pmux))) { - RTLIL::SigSpec sig_a = cell->getPort(ID(A)); - RTLIL::SigSpec sig_b = cell->getPort(ID(B)); + RTLIL::SigSpec sig_a = cell->getPort(ID::A); + RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_s = cell->getPort(ID(S)); - RTLIL::SigSpec sig_y = cell->getPort(ID(Y)); + RTLIL::SigSpec sig_y = cell->getPort(ID::Y); muxinfo_t muxinfo; muxinfo.cell = cell; @@ -227,10 +227,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->getPort(ID(A)); - RTLIL::SigSpec sig_b = mi.cell->getPort(ID(B)); + RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A); + RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B); RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S)); - RTLIL::SigSpec sig_y = mi.cell->getPort(ID(Y)); + RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y); RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -255,8 +255,8 @@ struct OptMuxtreeWorker } } - mi.cell->setPort(ID(A), new_sig_a); - mi.cell->setPort(ID(B), new_sig_b); + mi.cell->setPort(ID::A, new_sig_a); + mi.cell->setPort(ID::B, new_sig_b); mi.cell->setPort(ID(S), new_sig_s); if (GetSize(new_sig_s) == 1) { mi.cell->type = ID($mux); @@ -364,8 +364,8 @@ struct OptMuxtreeWorker int width = 0; idict<int> ctrl_bits; - if (portname == ID(B)) - width = GetSize(muxinfo.cell->getPort(ID(A))); + if (portname == ID::B) + width = GetSize(muxinfo.cell->getPort(ID::A)); for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false)) ctrl_bits(bit); @@ -414,8 +414,8 @@ struct OptMuxtreeWorker // set input ports to constants if we find known active or inactive signals if (do_replace_known) { - replace_known(knowledge, muxinfo, ID(A)); - replace_known(knowledge, muxinfo, ID(B)); + replace_known(knowledge, muxinfo, ID::A); + replace_known(knowledge, muxinfo, ID::B); } // if there is a constant activated port we just use it |