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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
commit | 956ecd48f71417b514c194a833a49238049e00b0 (patch) | |
tree | 468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/opt/opt_muxtree.cc | |
parent | 2d86563bb206748d6eef498eb27f7a004f20113d (diff) | |
download | yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.gz yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.bz2 yosys-956ecd48f71417b514c194a833a49238049e00b0.zip |
kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/opt/opt_muxtree.cc')
-rw-r--r-- | passes/opt/opt_muxtree.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 3c486bbcc..d076addae 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -88,7 +88,7 @@ struct OptMuxtreeWorker { RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_b = cell->getPort(ID::B); - RTLIL::SigSpec sig_s = cell->getPort(ID(S)); + RTLIL::SigSpec sig_s = cell->getPort(ID::S); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); muxinfo_t muxinfo; @@ -229,7 +229,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A); RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B); - RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S)); + RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S); RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y); RTLIL::SigSpec sig_ports = sig_b; @@ -257,12 +257,12 @@ struct OptMuxtreeWorker mi.cell->setPort(ID::A, new_sig_a); mi.cell->setPort(ID::B, new_sig_b); - mi.cell->setPort(ID(S), new_sig_s); + mi.cell->setPort(ID::S, new_sig_s); if (GetSize(new_sig_s) == 1) { mi.cell->type = ID($mux); - mi.cell->parameters.erase(ID(S_WIDTH)); + mi.cell->parameters.erase(ID::S_WIDTH); } else { - mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s)); + mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s)); } } } @@ -366,7 +366,7 @@ struct OptMuxtreeWorker idict<int> ctrl_bits; if (portname == ID::B) width = GetSize(muxinfo.cell->getPort(ID::A)); - for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false)) + for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false)) ctrl_bits(bit); int port_idx = 0, port_off = 0; |