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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/opt/opt_muxtree.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/opt/opt_muxtree.cc')
| -rw-r--r-- | passes/opt/opt_muxtree.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 3292a46c8..e844a4209 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -92,8 +92,8 @@ struct OptMuxtreeWorker muxinfo_t muxinfo; muxinfo.cell = cell; - for (int i = 0; i < sig_s.width; i++) { - RTLIL::SigSpec sig = sig_b.extract(i*sig_a.width, sig_a.width); + for (int i = 0; i < sig_s.__width; i++) { + RTLIL::SigSpec sig = sig_b.extract(i*sig_a.__width, sig_a.__width); RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1)); portinfo_t portinfo; for (int idx : sig2bits(sig)) { @@ -201,7 +201,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.width, sig_a.width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.__width, sig_a.__width); module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); module->cells.erase(mi.cell->name); delete mi.cell; @@ -211,7 +211,7 @@ struct OptMuxtreeWorker RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s; for (size_t i = 0; i < live_ports.size(); i++) { - RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.width, sig_a.width); + RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.__width, sig_a.__width); if (i == live_ports.size()-1) { new_sig_a = sig_in; } else { @@ -223,11 +223,11 @@ struct OptMuxtreeWorker mi.cell->connections["\\A"] = new_sig_a; mi.cell->connections["\\B"] = new_sig_b; mi.cell->connections["\\S"] = new_sig_s; - if (new_sig_s.width == 1) { + if (new_sig_s.__width == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); } else { - mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width); + mi.cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.__width); } } } @@ -260,7 +260,7 @@ struct OptMuxtreeWorker std::vector<int> results; assign_map.apply(sig); sig.expand(); - for (auto &c : sig.chunks) + for (auto &c : sig.__chunks) if (c.wire != NULL) { bitDef_t bit(c.wire, c.offset); if (bit2num.count(bit) == 0) { |