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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/opt/opt_muxtree.cc | |
parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) | |
download | yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.gz yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.bz2 yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.zip |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/opt/opt_muxtree.cc')
-rw-r--r-- | passes/opt/opt_muxtree.cc | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 750a9d417..33e66e077 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -88,10 +88,10 @@ struct OptMuxtreeWorker RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") { - RTLIL::SigSpec sig_a = cell->connections["\\A"]; - RTLIL::SigSpec sig_b = cell->connections["\\B"]; - RTLIL::SigSpec sig_s = cell->connections["\\S"]; - RTLIL::SigSpec sig_y = cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = cell->connections_["\\B"]; + RTLIL::SigSpec sig_s = cell->connections_["\\S"]; + RTLIL::SigSpec sig_y = cell->connections_["\\Y"]; muxinfo_t muxinfo; muxinfo.cell = cell; @@ -130,7 +130,7 @@ struct OptMuxtreeWorker } else { - for (auto &it : cell->connections) { + for (auto &it : cell->connections_) { for (int idx : sig2bits(it.second)) bit2info[idx].seen_non_mux = true; } @@ -194,10 +194,10 @@ struct OptMuxtreeWorker continue; } - RTLIL::SigSpec sig_a = mi.cell->connections["\\A"]; - RTLIL::SigSpec sig_b = mi.cell->connections["\\B"]; - RTLIL::SigSpec sig_s = mi.cell->connections["\\S"]; - RTLIL::SigSpec sig_y = mi.cell->connections["\\Y"]; + RTLIL::SigSpec sig_a = mi.cell->connections_["\\A"]; + RTLIL::SigSpec sig_b = mi.cell->connections_["\\B"]; + RTLIL::SigSpec sig_s = mi.cell->connections_["\\S"]; + RTLIL::SigSpec sig_y = mi.cell->connections_["\\Y"]; RTLIL::SigSpec sig_ports = sig_b; sig_ports.append(sig_a); @@ -205,7 +205,7 @@ struct OptMuxtreeWorker if (live_ports.size() == 1) { RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size()); - module->connections.push_back(RTLIL::SigSig(sig_y, sig_in)); + module->connections_.push_back(RTLIL::SigSig(sig_y, sig_in)); module->remove(mi.cell); } else @@ -222,9 +222,9 @@ struct OptMuxtreeWorker } } - mi.cell->connections["\\A"] = new_sig_a; - mi.cell->connections["\\B"] = new_sig_b; - mi.cell->connections["\\S"] = new_sig_s; + mi.cell->connections_["\\A"] = new_sig_a; + mi.cell->connections_["\\B"] = new_sig_b; + mi.cell->connections_["\\S"] = new_sig_s; if (new_sig_s.size() == 1) { mi.cell->type = "$mux"; mi.cell->parameters.erase("\\S_WIDTH"); |