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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
| commit | 1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9 (patch) | |
| tree | 7b7830c5da434964fd40792c393c45a31b8ad080 /passes/opt/opt_rmdff.cc | |
| parent | f20be90436b32e853d68c7e102a65d43f3843d91 (diff) | |
| parent | 3edb0abed88565447d5193f78261400655aa843a (diff) | |
| download | yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.gz yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.bz2 yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Diffstat (limited to 'passes/opt/opt_rmdff.cc')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 4ba61e512..0bf74098a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -347,8 +347,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) std::set<RTLIL::Cell*> muxes; mux_drivers.find(sig_d, muxes); for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID(A))); - RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID(B))); + RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID::B)); if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) { mod->connect(sig_q, sig_b); goto delete_dff; @@ -625,8 +625,8 @@ struct OptRmdffPass : public Pass { } if (cell->type.in(ID($mux), ID($pmux))) { - if (cell->getPort(ID(A)).size() == cell->getPort(ID(B)).size()) - mux_drivers.insert(assign_map(cell->getPort(ID(Y))), cell); + if (cell->getPort(ID::A).size() == cell->getPort(ID::B).size()) + mux_drivers.insert(assign_map(cell->getPort(ID::Y)), cell); continue; } |