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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-17 15:01:31 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-17 15:01:31 +0200 |
| commit | 8915f496d97a2e858cbadb265695dd1a54b80ac4 (patch) | |
| tree | 352bd2245f166e0f6679fed971655c7d3df0a7b4 /passes/opt/opt_rmdff.cc | |
| parent | 41191f1ea48437423b4caf81e6af1e3024bb8c7d (diff) | |
| parent | 3b19c3657cda6d972bd3b1c3eeacdfca5fb35de8 (diff) | |
| download | yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.tar.gz yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.tar.bz2 yosys-8915f496d97a2e858cbadb265695dd1a54b80ac4.zip | |
Merge pull request #1300 from YosysHQ/eddie/cleanup2
Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
Diffstat (limited to 'passes/opt/opt_rmdff.cc')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 4ba61e512..0bf74098a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -347,8 +347,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) std::set<RTLIL::Cell*> muxes; mux_drivers.find(sig_d, muxes); for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID(A))); - RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID(B))); + RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID::B)); if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) { mod->connect(sig_q, sig_b); goto delete_dff; @@ -625,8 +625,8 @@ struct OptRmdffPass : public Pass { } if (cell->type.in(ID($mux), ID($pmux))) { - if (cell->getPort(ID(A)).size() == cell->getPort(ID(B)).size()) - mux_drivers.insert(assign_map(cell->getPort(ID(Y))), cell); + if (cell->getPort(ID::A).size() == cell->getPort(ID::B).size()) + mux_drivers.insert(assign_map(cell->getPort(ID::Y)), cell); continue; } |