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| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-17 10:07:05 -0800 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-17 10:07:05 -0800 |
| commit | f2ee57f79875e8c63d5da9aedd7c33fc847e6977 (patch) | |
| tree | 7650d4822f935efd2b8b0a3f356b7f95760390ec /passes/opt/opt_rmdff.cc | |
| parent | 2d7bcaf2f2ddfaa3b206421513a6fb44077f5824 (diff) | |
| parent | 6170cfe9cddfd0040fa9f7b535d25dd2c99cdb91 (diff) | |
| download | yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.tar.gz yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.tar.bz2 yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.zip | |
Merge pull request #4 from cliffordwolf/master
verilog defaults
Diffstat (limited to 'passes/opt/opt_rmdff.cc')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index a84bf4376..9ce98004e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -92,6 +92,12 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } + if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) { + RTLIL::SigSig conn(sig_q, val_rv); + mod->connections.push_back(conn); + goto delete_dff; + } + if (sig_d.is_fully_const() && sig_r.width == 0) { RTLIL::SigSig conn(sig_q, sig_d); mod->connections.push_back(conn); |