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| author | Xiretza <xiretza@xiretza.xyz> | 2020-04-21 12:51:58 +0200 |
|---|---|---|
| committer | Xiretza <xiretza@xiretza.xyz> | 2020-05-28 22:59:04 +0200 |
| commit | edd8ff2c0778d97808869488cc7394151456c4ca (patch) | |
| tree | 797418b87588ae7a69992b7f107dfd5cdfdec08d /passes/opt/opt_share.cc | |
| parent | 17163cf43a6b6eec9aac44f6a4463dda54b8ed68 (diff) | |
| download | yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.gz yosys-edd8ff2c0778d97808869488cc7394151456c4ca.tar.bz2 yosys-edd8ff2c0778d97808869488cc7394151456c4ca.zip | |
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
Diffstat (limited to 'passes/opt/opt_share.cc')
| -rw-r--r-- | passes/opt/opt_share.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index b08a8172f..cbace7bac 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -103,7 +103,7 @@ bool cell_supported(RTLIL::Cell *cell) if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci) return true; - } else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($concat))) { + } else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat))) { return true; } @@ -130,7 +130,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b) RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name) { - if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B) + if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B) return port_name; return ""; |