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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-21 19:44:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-21 19:44:08 +0200 |
| commit | 13117bb346dd02d2345f716b4403239aebe3d0e2 (patch) | |
| tree | 0878b6b5a3b563de681a89d5f3ec30a388a29a47 /passes/opt/share.cc | |
| parent | 96e821dc6cf170168218fa4cddc7c9ddafd6f439 (diff) | |
| download | yosys-13117bb346dd02d2345f716b4403239aebe3d0e2.tar.gz yosys-13117bb346dd02d2345f716b4403239aebe3d0e2.tar.bz2 yosys-13117bb346dd02d2345f716b4403239aebe3d0e2.zip | |
Re-enabled assert for new logic loops in "share" pass
Diffstat (limited to 'passes/opt/share.cc')
| -rw-r--r-- | passes/opt/share.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc index e3b0159c0..74b049bb6 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1055,10 +1055,7 @@ struct ShareWorker log_assert(recursion_state.empty()); bool after_scc = before_scc || module_has_scc(); - if (before_scc != after_scc) - log("Warning: introduced topological logic loops!\n"); - // Pass::call_on_module(design, module, "scc;; show"); - // log_assert(before_scc == after_scc); + log_assert(before_scc == after_scc); } }; |