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| author | Jannis Harder <me@jix.one> | 2022-08-16 14:18:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-16 14:18:35 +0200 |
| commit | 556d008ed3c2db351e93e0075ccd47bdfb634fd9 (patch) | |
| tree | ab23fa7355df8f8ead24839ee7846e68cdbfb935 /passes/opt/wreduce.cc | |
| parent | c26b2bf543a226e65a3fb07040bb278d668accf2 (diff) | |
| parent | f7023d06a2bda56467c8f07cc44d3b92f0eab2ba (diff) | |
| download | yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.gz yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.bz2 yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.zip | |
Merge pull request #3434 from jix/witness_flow
Updated formal flow with new witness format
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 08ab6de6f..8fd4c788c 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -166,8 +166,8 @@ struct WreduceWorker for (int i = GetSize(sig_q)-1; i >= 0; i--) { - if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) && - (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) { + if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || (!config->keepdc && initval[i] == State::Sx)) && + (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || (!config->keepdc && rst_value[i] == State::Sx))) { module->connect(sig_q[i], State::S0); initvals.remove_init(sig_q[i]); sig_d.remove(i); @@ -175,8 +175,8 @@ struct WreduceWorker continue; } - if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && - (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) { + if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && (!config->keepdc || initval[i] != State::Sx) && + (!has_reset || i >= GetSize(rst_value) || (rst_value[i] == rst_value[i-1] && (!config->keepdc || rst_value[i] != State::Sx)))) { module->connect(sig_q[i], sig_q[i-1]); initvals.remove_init(sig_q[i]); sig_d.remove(i); |