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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 13:37:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-23 13:37:53 -0700 |
| commit | 68359bcd6f1ded0dffa12f0d1e2288e433fd83e7 (patch) | |
| tree | 6cbf1976a4a7ca510e7330c8f6d09603d9dc9446 /passes/opt/wreduce.cc | |
| parent | ae89e6ab26d2d87a604e20ebc14dcda8c9901585 (diff) | |
| parent | 5ac7e38d0aab1c73150accd9befbccc5398b8e42 (diff) | |
| download | yosys-68359bcd6f1ded0dffa12f0d1e2288e433fd83e7.tar.gz yosys-68359bcd6f1ded0dffa12f0d1e2288e433fd83e7.tar.bz2 yosys-68359bcd6f1ded0dffa12f0d1e2288e433fd83e7.zip | |
Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 96a77c119..cfe4b4067 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -29,6 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct WreduceConfig { pool<IdString> supported_cell_types; + bool keepdc = false; WreduceConfig() { @@ -82,7 +83,7 @@ struct WreduceWorker SigBit ref = sig_a[i]; for (int k = 0; k < GetSize(sig_s); k++) { - if (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx && ref != sig_b[k*GetSize(sig_a) + i]) + if ((config->keepdc || (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx)) && ref != sig_b[k*GetSize(sig_a) + i]) goto no_match_ab; if (sig_b[k*GetSize(sig_a) + i] != Sx) ref = sig_b[k*GetSize(sig_a) + i]; @@ -497,6 +498,9 @@ struct WreducePass : public Pass { log(" Do not change the width of memory address ports. Use this options in\n"); log(" flows that use the 'memory_memx' pass.\n"); log("\n"); + log(" -keepdc\n"); + log(" Do not optimize explicit don't-care values.\n"); + log("\n"); } void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE { @@ -511,6 +515,10 @@ struct WreducePass : public Pass { opt_memx = true; continue; } + if (args[argidx] == "-keepdc") { + config.keepdc = true; + continue; + } break; } extra_args(args, argidx, design); |