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authorArchie <ac11018@ic.ac.uk>2022-08-21 17:18:20 -0500
committerArchie <ac11018@ic.ac.uk>2022-08-21 17:18:20 -0500
commitdb73f3c26b2768f93c7573b7c7d74b1cc7a0756d (patch)
tree81696fd98770e519aea96fe3a6e40bcc3b3a4360 /passes/opt/wreduce.cc
parente7e8e3b0f65ea1ebfcf04bffd0d9ba90f8e0d7fe (diff)
parent029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff)
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Merge branch 'master' of https://github.com/ALGCDG/yosys
Diffstat (limited to 'passes/opt/wreduce.cc')
-rw-r--r--passes/opt/wreduce.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 08ab6de6f..8fd4c788c 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -166,8 +166,8 @@ struct WreduceWorker
for (int i = GetSize(sig_q)-1; i >= 0; i--)
{
- if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
- (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
+ if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || (!config->keepdc && initval[i] == State::Sx)) &&
+ (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || (!config->keepdc && rst_value[i] == State::Sx))) {
module->connect(sig_q[i], State::S0);
initvals.remove_init(sig_q[i]);
sig_d.remove(i);
@@ -175,8 +175,8 @@ struct WreduceWorker
continue;
}
- if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
- (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
+ if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && (!config->keepdc || initval[i] != State::Sx) &&
+ (!has_reset || i >= GetSize(rst_value) || (rst_value[i] == rst_value[i-1] && (!config->keepdc || rst_value[i] != State::Sx)))) {
module->connect(sig_q[i], sig_q[i-1]);
initvals.remove_init(sig_q[i]);
sig_d.remove(i);