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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 14:03:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 14:03:34 -0700 |
| commit | e87916b7eb7dd9fccaab19f7d494f44bdfb929f5 (patch) | |
| tree | 9050bee3d21de884fb5eb70b3cea0dc6832fc2fe /passes/opt/wreduce.cc | |
| parent | 8791e0caac279dd1ca04e93ba8d0175f3cc70f91 (diff) | |
| parent | c926eeb43a9c42a0ecc34871f383f4181b7a45f9 (diff) | |
| download | yosys-e87916b7eb7dd9fccaab19f7d494f44bdfb929f5.tar.gz yosys-e87916b7eb7dd9fccaab19f7d494f44bdfb929f5.tar.bz2 yosys-e87916b7eb7dd9fccaab19f7d494f44bdfb929f5.zip | |
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index dff1c5370..908a85d5b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -366,13 +366,13 @@ struct WreduceWorker } if (cell->type.in("$add", "$sub")) { - SigSpec A = cell->getPort("\\A"); - SigSpec B = cell->getPort("\\B"); + SigSpec A = mi.sigmap(cell->getPort("\\A")); + SigSpec B = mi.sigmap(cell->getPort("\\B")); bool sub = cell->type == "$sub"; int i; for (i = 0; i < GetSize(sig); i++) { - if (B[i] != S0 && (sub || A[i] != S0)) + if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0)) break; if (B[i] == S0) module->connect(sig[i], A[i]); @@ -395,7 +395,7 @@ struct WreduceWorker } if (bits_removed) { - log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", + log("Removed %d bits (of %d) from port Y of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); did_something = true; |