initial import

9 files changed, 1637 insertions, 0 deletions

diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc
new file mode 100644
index 000000000..3602b96bd
--- /dev/null
+++ b/passes/opt/Makefile.inc
@@ -0,0 +1,9 @@
+
+OBJS += passes/opt/opt.o
+OBJS += passes/opt/opt_share.o
+OBJS += passes/opt/opt_muxtree.o
+OBJS += passes/opt/opt_reduce.o
+OBJS += passes/opt/opt_rmdff.o
+OBJS += passes/opt/opt_rmunused.o 
+OBJS += passes/opt/opt_const.o 
+
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
new file mode 100644
index 000000000..9e33f78ca
--- /dev/null
+++ b/passes/opt/opt.cc
@@ -0,0 +1,62 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+bool OPT_DID_SOMETHING;
+
+struct OptPass : public Pass {
+	OptPass() : Pass("opt") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT pass (performing simple optimizations).\n");
+		log_push();
+
+		extra_args(args, 1, design);
+
+		log_header("Optimizing in-memory representation of design.\n");
+		design->optimize();
+
+		Pass::call(design, "opt_const");
+		Pass::call(design, "opt_share -nomux");
+		while (1) {
+			OPT_DID_SOMETHING = false;
+			Pass::call(design, "opt_muxtree");
+			Pass::call(design, "opt_reduce");
+			Pass::call(design, "opt_share");
+			Pass::call(design, "opt_rmdff");
+			Pass::call(design, "opt_rmunused");
+			Pass::call(design, "opt_const");
+			if (OPT_DID_SOMETHING == false)
+				break;
+			log_header("Rerunning OPT passes. (Maybe there is more to do..)\n");
+		}
+
+		log_header("Optimizing in-memory representation of design.\n");
+		design->optimize();
+
+		log_header("Finished OPT passes. (There is nothing left to do.)\n");
+		log_pop();
+	}
+} OptPass;
+ 
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
new file mode 100644
index 000000000..9edea6709
--- /dev/null
+++ b/passes/opt/opt_const.cc
@@ -0,0 +1,263 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#undef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <stdio.h>
+#include <set>
+
+bool did_something;
+
+void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
+{
+	RTLIL::SigSpec Y = cell->connections[out_port];
+	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
+			cell->type.c_str(), cell->name.c_str(), info.c_str(),
+			module->name.c_str(), log_signal(Y), log_signal(out_val));
+	OPT_DID_SOMETHING = true;
+	// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
+	module->connections.push_back(RTLIL::SigSig(Y, out_val));
+	module->cells.erase(cell->name);
+	delete cell;
+	did_something = true;
+}
+
+void replace_const_cells(RTLIL::Module *module)
+{
+	SigMap assign_map(module);
+
+	std::vector<RTLIL::Cell*> cells;
+	cells.reserve(module->cells.size());
+	for (auto &cell_it : module->cells)
+		cells.push_back(cell_it.second);
+
+	for (auto cell : cells)
+	{
+#define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
+#define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_))
+
+		if (cell->type == "$_INV_") {
+			RTLIL::SigSpec input = cell->connections["\\A"];
+			assign_map.apply(input);
+			if (input.match("1")) ACTION_DO_Y(0);
+			if (input.match("0")) ACTION_DO_Y(1);
+			if (input.match("*")) ACTION_DO_Y(x);
+		}
+
+		if (cell->type == "$_AND_") {
+			RTLIL::SigSpec input;
+			input.append(cell->connections["\\B"]);
+			input.append(cell->connections["\\A"]);
+			assign_map.apply(input);
+			if (input.match(" 0")) ACTION_DO_Y(0);
+			if (input.match("0 ")) ACTION_DO_Y(0);
+			if (input.match("11")) ACTION_DO_Y(1);
+			if (input.match(" *")) ACTION_DO_Y(x);
+			if (input.match("* ")) ACTION_DO_Y(x);
+		}
+
+		if (cell->type == "$_OR_") {
+			RTLIL::SigSpec input;
+			input.append(cell->connections["\\B"]);
+			input.append(cell->connections["\\A"]);
+			assign_map.apply(input);
+			if (input.match(" 1")) ACTION_DO_Y(1);
+			if (input.match("1 ")) ACTION_DO_Y(1);
+			if (input.match("00")) ACTION_DO_Y(0);
+			if (input.match(" *")) ACTION_DO_Y(x);
+			if (input.match("* ")) ACTION_DO_Y(x);
+		}
+
+		if (cell->type == "$_XOR_") {
+			RTLIL::SigSpec input;
+			input.append(cell->connections["\\B"]);
+			input.append(cell->connections["\\A"]);
+			assign_map.apply(input);
+			if (input.match("00")) ACTION_DO_Y(0);
+			if (input.match("01")) ACTION_DO_Y(1);
+			if (input.match("10")) ACTION_DO_Y(1);
+			if (input.match("11")) ACTION_DO_Y(0);
+			if (input.match(" *")) ACTION_DO_Y(x);
+			if (input.match("* ")) ACTION_DO_Y(x);
+		}
+
+		if (cell->type == "$_MUX_") {
+			RTLIL::SigSpec input;
+			input.append(cell->connections["\\S"]);
+			input.append(cell->connections["\\B"]);
+			input.append(cell->connections["\\A"]);
+			assign_map.apply(input);
+			if (input.extract(2, 1) == input.extract(1, 1))
+				ACTION_DO("\\Y", input.extract(2, 1));
+			if (input.match("  0")) ACTION_DO("\\Y", input.extract(2, 1));
+			if (input.match("  1")) ACTION_DO("\\Y", input.extract(1, 1));
+#ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
+			if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
+			if (input.match("  *")) ACTION_DO_Y(x);
+#endif
+		}
+
+		if (cell->type == "$eq" || cell->type == "$ne")
+		{
+			if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
+				int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
+				cell->connections["\\A"].extend(width, cell->parameters["\\A_SIGNED"].as_bool());
+				cell->connections["\\B"].extend(width, cell->parameters["\\B_SIGNED"].as_bool());
+				cell->parameters["\\A_WIDTH"] = width;
+				cell->parameters["\\B_WIDTH"] = width;
+			}
+
+			RTLIL::SigSpec a = cell->connections["\\A"];
+			RTLIL::SigSpec b = cell->connections["\\B"];
+			RTLIL::SigSpec new_a, new_b;
+			a.expand(), b.expand();
+
+			assert(a.chunks.size() == b.chunks.size());
+			for (size_t i = 0; i < a.chunks.size(); i++) {
+				if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
+					continue;
+				if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
+					continue;
+				new_a.append(a.chunks[i]);
+				new_b.append(b.chunks[i]);
+			}
+
+			if (new_a.width != a.width) {
+				new_a.optimize();
+				new_b.optimize();
+				cell->connections["\\A"] = new_a;
+				cell->connections["\\B"] = new_b;
+				cell->parameters["\\A_WIDTH"] = new_a.width;
+				cell->parameters["\\B_WIDTH"] = new_b.width;
+			}
+
+			if (new_a.width == 0) {
+				replace_cell(module, cell, "empty", "\\Y", RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0));
+				goto next_cell;
+			}
+		}
+
+#define FOLD_1ARG_CELL(_t) \
+		if (cell->type == "$" #_t) { \
+			RTLIL::SigSpec a = cell->connections["\\A"]; \
+			assign_map.apply(a); \
+			if (a.is_fully_const()) { \
+				a.optimize(); \
+				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \
+						cell->parameters["\\A_SIGNED"].as_bool(), false, \
+						cell->parameters["\\Y_WIDTH"].as_int())); \
+				replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
+				goto next_cell; \
+			} \
+		}
+#define FOLD_2ARG_CELL(_t) \
+		if (cell->type == "$" #_t) { \
+			RTLIL::SigSpec a = cell->connections["\\A"]; \
+			RTLIL::SigSpec b = cell->connections["\\B"]; \
+			assign_map.apply(a), assign_map.apply(b); \
+			if (a.is_fully_const() && b.is_fully_const()) { \
+				a.optimize(), b.optimize(); \
+				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \
+						cell->parameters["\\A_SIGNED"].as_bool(), \
+						cell->parameters["\\B_SIGNED"].as_bool(), \
+						cell->parameters["\\Y_WIDTH"].as_int())); \
+				replace_cell(module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \
+				goto next_cell; \
+			} \
+		}
+
+		FOLD_1ARG_CELL(not)
+		FOLD_2ARG_CELL(and)
+		FOLD_2ARG_CELL(or)
+		FOLD_2ARG_CELL(xor)
+		FOLD_2ARG_CELL(xnor)
+
+		FOLD_1ARG_CELL(reduce_and)
+		FOLD_1ARG_CELL(reduce_or)
+		FOLD_1ARG_CELL(reduce_xor)
+		FOLD_1ARG_CELL(reduce_xnor)
+		FOLD_1ARG_CELL(reduce_bool)
+
+		FOLD_1ARG_CELL(logic_not)
+		FOLD_2ARG_CELL(logic_and)
+		FOLD_2ARG_CELL(logic_or)
+
+		FOLD_2ARG_CELL(shl)
+		FOLD_2ARG_CELL(shr)
+		FOLD_2ARG_CELL(sshl)
+		FOLD_2ARG_CELL(sshr)
+
+		FOLD_2ARG_CELL(lt)
+		FOLD_2ARG_CELL(le)
+		FOLD_2ARG_CELL(eq)
+		FOLD_2ARG_CELL(ne)
+		FOLD_2ARG_CELL(gt)
+		FOLD_2ARG_CELL(ge)
+
+		FOLD_2ARG_CELL(add)
+		FOLD_2ARG_CELL(sub)
+		FOLD_2ARG_CELL(mul)
+		FOLD_2ARG_CELL(div)
+		FOLD_2ARG_CELL(mod)
+		FOLD_2ARG_CELL(pow)
+
+		FOLD_1ARG_CELL(pos)
+		FOLD_1ARG_CELL(neg)
+
+		if (cell->type == "$mux") {
+			RTLIL::SigSpec input = cell->connections["\\S"];
+			assign_map.apply(input);
+			if (input.is_fully_const())
+				ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]);
+		}
+
+	next_cell:;
+#undef ACTION_DO
+#undef ACTION_DO_Y
+#undef FOLD_1ARG_CELL
+#undef FOLD_2ARG_CELL
+	}
+}
+
+struct OptConstPass : public Pass {
+	OptConstPass() : Pass("opt_const") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT_CONST pass (perform const folding).\n");
+		log_push();
+
+		extra_args(args, 1, design);
+
+		for (auto &mod_it : design->modules)
+			do {
+				did_something = false;
+				replace_const_cells(mod_it.second);
+			} while (did_something);
+
+		log_pop();
+	}
+} OptConstPass;
+
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
new file mode 100644
index 000000000..d1f4e7b10
--- /dev/null
+++ b/passes/opt/opt_muxtree.cc
@@ -0,0 +1,417 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include "kernel/celltypes.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <stdio.h>
+#include <set>
+
+struct OptMuxtreeWorker
+{
+	RTLIL::Design *design;
+	RTLIL::Module *module;
+	SigMap assign_map;
+	int removed_count;
+
+	typedef std::pair<RTLIL::Wire*,int> bitDef_t;
+
+	struct bitinfo_t {
+		int num;
+		bitDef_t bit;
+		bool seen_non_mux;
+		std::vector<int> mux_users;
+		std::vector<int> mux_drivers;
+	};
+
+	std::map<bitDef_t, int> bit2num;
+	std::vector<bitinfo_t> bit2info;
+
+	struct portinfo_t {
+		std::vector<int> ctrl_sigs;
+		std::vector<int> input_sigs;
+		std::vector<int> input_muxes;
+		bool const_activated;
+		bool enabled;
+	};
+
+	struct muxinfo_t {
+		RTLIL::Cell *cell;
+		std::vector<portinfo_t> ports;
+	};
+
+	std::vector<muxinfo_t> mux2info;
+
+	OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
+			design(design), module(module), assign_map(module), removed_count(0)
+	{
+		log("Running muxtree optimizier on module %s..\n", module->name.c_str());
+
+		log("  Creating internal representation of mux trees.\n");
+
+		// Populate bit2info[]:
+		//	.seen_non_mux
+		//	.mux_users
+		//	.mux_drivers
+		// Populate mux2info[].ports[]:
+		//	.ctrl_sigs
+		//	.input_sigs
+		//	.const_activated
+		for (auto &cell_it : module->cells)
+		{
+			RTLIL::Cell *cell = cell_it.second;
+			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
+			{
+				RTLIL::SigSpec sig_a = cell->connections["\\A"];
+				RTLIL::SigSpec sig_b = cell->connections["\\B"];
+				RTLIL::SigSpec sig_s = cell->connections["\\S"];
+				RTLIL::SigSpec sig_y = cell->connections["\\Y"];
+
+				muxinfo_t muxinfo;
+				muxinfo.cell = cell;
+
+				for (int i = 0; i < sig_s.width; i++) {
+					RTLIL::SigSpec sig = sig_b.extract(i*sig_a.width, sig_a.width);
+					RTLIL::SigSpec ctrl_sig = assign_map(sig_s.extract(i, 1));
+					portinfo_t portinfo;
+					for (int idx : sig2bits(sig)) {
+						add_to_list(bit2info[idx].mux_users, mux2info.size());
+						add_to_list(portinfo.input_sigs, idx);
+					}
+					for (int idx : sig2bits(ctrl_sig))
+						add_to_list(portinfo.ctrl_sigs, idx);
+					portinfo.const_activated = ctrl_sig.is_fully_const() && ctrl_sig.as_bool();
+					portinfo.enabled = false;
+					muxinfo.ports.push_back(portinfo);
+				}
+
+				portinfo_t portinfo;
+				for (int idx : sig2bits(sig_a)) {
+					add_to_list(bit2info[idx].mux_users, mux2info.size());
+					add_to_list(portinfo.input_sigs, idx);
+				}
+				portinfo.const_activated = false;
+				portinfo.enabled = false;
+				muxinfo.ports.push_back(portinfo);
+
+				for (int idx : sig2bits(sig_y))
+					add_to_list(bit2info[idx].mux_drivers, mux2info.size());
+
+				for (int idx : sig2bits(sig_s))
+					bit2info[idx].seen_non_mux = true;
+
+				mux2info.push_back(muxinfo);
+			}
+			else
+			{
+				for (auto &it : cell->connections) {
+					for (int idx : sig2bits(it.second))
+						bit2info[idx].seen_non_mux = true;
+				}
+			}
+		}
+		for (auto &it : module->wires) {
+			if (it.second->port_output)
+				for (int idx : sig2bits(RTLIL::SigSpec(it.second)))
+					bit2info[idx].seen_non_mux = true;
+		}
+
+		if (mux2info.size() == 0) {
+			log("  No muxes found in this module.\n");
+			return;
+		}
+
+		// Populate mux2info[].ports[]:
+		//	.input_muxes
+		for (size_t i = 0; i < bit2info.size(); i++)
+		for (int j : bit2info[i].mux_users)
+		for (auto &p : mux2info[j].ports) {
+			if (is_in_list(p.input_sigs, i))
+				for (int k : bit2info[i].mux_drivers)
+					add_to_list(p.input_muxes, k);
+		}
+
+		log("  Evaluating internal representation of mux trees.\n");
+
+		std::set<int> root_muxes;
+		for (auto &bi : bit2info) {
+			if (!bi.seen_non_mux)
+				continue;
+			for (int mux_idx : bi.mux_drivers)
+				root_muxes.insert(mux_idx);
+		}
+		for (int mux_idx : root_muxes)
+			eval_root_mux(mux_idx);
+
+		log("  Analyzing evaluation results.\n");
+
+		for (auto &mi : mux2info)
+		{
+			std::vector<int> live_ports;
+			for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) {
+				portinfo_t &pi = mi.ports[port_idx];
+				if (pi.enabled) {
+					live_ports.push_back(port_idx);
+				} else {
+					log("    dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(),
+							mi.cell->type.c_str(), mi.cell->name.c_str());
+					OPT_DID_SOMETHING = true;
+					removed_count++;
+				}
+			}
+
+			if (live_ports.size() == mi.ports.size())
+				continue;
+
+			if (live_ports.size() == 0) {
+				module->cells.erase(mi.cell->name);
+				delete mi.cell;
+				continue;
+			}
+
+			RTLIL::SigSpec sig_a = mi.cell->connections["\\A"];
+			RTLIL::SigSpec sig_b = mi.cell->connections["\\B"];
+			RTLIL::SigSpec sig_s = mi.cell->connections["\\S"];
+			RTLIL::SigSpec sig_y = mi.cell->connections["\\Y"];
+
+			RTLIL::SigSpec sig_ports = sig_b;
+			sig_ports.append(sig_a);
+
+			if (live_ports.size() == 1)
+			{
+				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.width, sig_a.width);
+				module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
+				module->cells.erase(mi.cell->name);
+				delete mi.cell;
+			}
+			else
+			{
+				RTLIL::SigSpec new_sig_a, new_sig_b, new_sig_s;
+
+				for (size_t i = 0; i < live_ports.size(); i++) {
+					RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[i]*sig_a.width, sig_a.width);
+					if (i == live_ports.size()-1) {
+						new_sig_a = sig_in;
+					} else {
+						new_sig_b.append(sig_in);
+						new_sig_s.append(sig_s.extract(live_ports[i], 1));
+					}
+				}
+
+				mi.cell->connections["\\A"] = new_sig_a;
+				mi.cell->connections["\\B"] = new_sig_b;
+				mi.cell->connections["\\S"] = new_sig_s;
+				if (new_sig_s.width == 1) {
+					mi.cell->type = "$mux";
+					mi.cell->attributes.erase("\\S_WIDTH");
+				} else {
+					mi.cell->attributes["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
+				}
+			}
+		}
+	}
+
+	bool list_is_subset(const std::vector<int> &sub, const std::vector<int> &super)
+	{
+		for (int v : sub)
+			if (!is_in_list(super, v))
+				return false;
+		return true;
+	}
+
+	bool is_in_list(const std::vector<int> &list, int value)
+	{
+		for (int v : list)
+			if (v == value)
+				return true;
+		return false;
+	}
+
+	void add_to_list(std::vector<int> &list, int value)
+	{
+		if (!is_in_list(list, value))
+			list.push_back(value);
+	}
+
+	std::vector<int> sig2bits(RTLIL::SigSpec sig)
+	{
+		std::vector<int> results;
+		assign_map.apply(sig);
+		sig.expand();
+		for (auto &c : sig.chunks)
+			if (c.wire != NULL) {
+				bitDef_t bit(c.wire, c.offset);
+				if (bit2num.count(bit) == 0) {
+					bitinfo_t info;
+					info.num = bit2info.size();
+					info.bit = bit;
+					info.seen_non_mux = false;
+					bit2info.push_back(info);
+					bit2num[info.bit] = info.num;
+				}
+				results.push_back(bit2num[bit]);
+			}
+		return results;
+	}
+
+	struct knowledge_t
+	{
+		// database of known inactive signals
+		// the 2nd integer is a reference counter used to manage the
+		// list. when it is non-zero the signal in known to be inactive
+		std::map<int, int> known_inactive;
+
+		// database of known active signals
+		// the 2nd dimension is the list of or-ed signals. so we know that
+		// for each i there is a j so that known_active[i][j] points to an
+		// inactive control signal.
+		std::vector<std::vector<int>> known_active;
+
+		// this is just used to keep track of visited muxes in order to prohibit
+		// endless recursion in mux loops
+		std::set<int> visited_muxes;
+	};
+
+	void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx)
+	{
+		muxinfo_t &muxinfo = mux2info[mux_idx];
+		muxinfo.ports[port_idx].enabled = true;
+
+		for (size_t i = 0; i < muxinfo.ports.size(); i++) {
+			if (int(i) == port_idx)
+				continue;
+			for (int b : muxinfo.ports[i].ctrl_sigs)
+				knowledge.known_inactive[b]++;
+		}
+
+		if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
+			knowledge.known_active.push_back(muxinfo.ports[port_idx].ctrl_sigs);
+
+		for (int m : muxinfo.ports[port_idx].input_muxes) {
+			if (knowledge.visited_muxes.count(m) > 0)
+				continue;
+			knowledge.visited_muxes.insert(m);
+			eval_mux(knowledge, m);
+			knowledge.visited_muxes.erase(m);
+		}
+
+		if (port_idx < int(muxinfo.ports.size())-1 && !muxinfo.ports[port_idx].const_activated)
+			knowledge.known_active.pop_back();
+
+		for (size_t i = 0; i < muxinfo.ports.size(); i++) {
+			if (int(i) == port_idx)
+				continue;
+			for (int b : muxinfo.ports[i].ctrl_sigs)
+				knowledge.known_inactive[b]--;
+		}
+	}
+
+	void eval_mux(knowledge_t &knowledge, int mux_idx)
+	{
+		muxinfo_t &muxinfo = mux2info[mux_idx];
+
+		// if there is a constant activated port we just use it
+		for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
+		{
+			portinfo_t &portinfo = muxinfo.ports[port_idx];
+			if (portinfo.const_activated) {
+				eval_mux_port(knowledge, mux_idx, port_idx);
+				return;
+			}
+		}
+
+		// compare ports with known_active signals. if we find a match, only this
+		// port can be active. do not include the last port (its the default port
+		// that has no control signals).
+		for (size_t port_idx = 0; port_idx < muxinfo.ports.size()-1; port_idx++)
+		{
+			portinfo_t &portinfo = muxinfo.ports[port_idx];
+			for (size_t i = 0; i < knowledge.known_active.size(); i++) {
+				if (list_is_subset(knowledge.known_active[i], portinfo.ctrl_sigs)) {
+					eval_mux_port(knowledge, mux_idx, port_idx);
+					return;
+				}
+			}
+		}
+
+		// compare ports with known_inactive and known_active signals. If all control
+		// signals of the port are know_inactive or if the control signals of all other
+		// ports are known_active this port can't be activated. this loop includes the
+		// default port but no known_inactive match is performed on the default port.
+		for (size_t port_idx = 0; port_idx < muxinfo.ports.size(); port_idx++)
+		{
+			portinfo_t &portinfo = muxinfo.ports[port_idx];
+
+			if (port_idx < muxinfo.ports.size()-1) {
+				bool found_non_known_inactive = false;
+				for (int i : portinfo.ctrl_sigs)
+					if (knowledge.known_inactive[i] == 0)
+						found_non_known_inactive = true;
+				if (!found_non_known_inactive)
+					continue;
+			}
+
+			bool port_active = true;
+			std::vector<int> other_ctrl_sig;
+			for (size_t i = 0; i < muxinfo.ports.size()-1; i++) {
+				if (i == port_idx)
+					continue;
+				other_ctrl_sig.insert(other_ctrl_sig.end(),
+						muxinfo.ports[i].ctrl_sigs.begin(), muxinfo.ports[i].ctrl_sigs.end());
+			}
+			for (size_t i = 0; i < knowledge.known_active.size(); i++) {
+				if (list_is_subset(knowledge.known_active[i], other_ctrl_sig))
+					port_active = false;
+			}
+			if (port_active)
+				eval_mux_port(knowledge, mux_idx, port_idx);
+		}
+	}
+
+	void eval_root_mux(int mux_idx)
+	{
+		knowledge_t knowledge;
+		eval_mux(knowledge, mux_idx);
+	}
+};
+
+struct OptMuxtreePass : public Pass {
+	OptMuxtreePass() : Pass("opt_muxtree") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
+		extra_args(args, 1, design);
+
+		int total_count = 0;
+		for (auto &mod_it : design->modules) {
+			if (mod_it.second->processes.size() > 0) {
+				log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+			} else {
+				OptMuxtreeWorker worker(design, mod_it.second);
+				total_count += worker.removed_count;
+			}
+		}
+		log("Removed %d multiplexer ports.\n", total_count);
+	}
+} OptMuxtreePass;
+ 
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
new file mode 100644
index 000000000..9a1b263a0
--- /dev/null
+++ b/passes/opt/opt_reduce.cc
@@ -0,0 +1,236 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include "kernel/sha1.h"
+#include "kernel/celltypes.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <stdio.h>
+#include <set>
+
+struct OptReduceWorker
+{
+	RTLIL::Design *design;
+	RTLIL::Module *module;
+	SigMap assign_map;
+
+	int total_count;
+	bool did_something;
+
+	void opt_reduce(std::set<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
+	{
+		if (cells.count(cell) == 0)
+			return;
+		cells.erase(cell);
+
+		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
+		sig_a.sort_and_unify();
+		sig_a.expand();
+
+		RTLIL::SigSpec new_sig_a;
+		for (auto &chunk : sig_a.chunks)
+		{
+			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
+				if (cell->type == "$reduce_and") {
+					new_sig_a = RTLIL::SigSpec(RTLIL::State::S0);
+					break;
+				}
+				continue;
+			}
+			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) {
+				if (cell->type == "$reduce_or") {
+					new_sig_a = RTLIL::SigSpec(RTLIL::State::S1);
+					break;
+				}
+				continue;
+			}
+			if (chunk.wire == NULL) {
+				new_sig_a = RTLIL::SigSpec(RTLIL::State::Sx);
+				break;
+			}
+
+			bool imported_children = false;
+			for (auto child_cell : drivers.find(chunk)) {
+				if (child_cell->type == cell->type) {
+					opt_reduce(cells, drivers, child_cell);
+					new_sig_a.append(child_cell->connections["\\A"]);
+					imported_children = true;
+				}
+			}
+			if (!imported_children)
+				new_sig_a.append(chunk);
+		}
+		new_sig_a.sort_and_unify();
+
+		if (new_sig_a != sig_a || sig_a.width != cell->connections["\\A"].width) {
+			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
+			did_something = true;
+			OPT_DID_SOMETHING = true;
+			total_count++;
+		}
+
+		cell->connections["\\A"] = new_sig_a;
+		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.width);
+		return;
+	}
+
+	void opt_mux(RTLIL::Cell *cell)
+	{
+		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
+		RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
+		RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]);
+
+		RTLIL::SigSpec new_sig_b, new_sig_s;
+		std::set<RTLIL::SigSpec> handled_sig;
+
+		handled_sig.insert(sig_a);
+		for (int i = 0; i < sig_s.width; i++)
+		{
+			RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.width, sig_a.width);
+			if (handled_sig.count(this_b) > 0)
+				continue;
+
+			RTLIL::SigSpec this_s = sig_s.extract(i, 1);
+			for (int j = i+1; j < sig_s.width; j++) {
+				RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.width, sig_a.width);
+				if (this_b == that_b)
+					this_s.append(sig_s.extract(j, 1));
+			}
+
+			if (this_s.width > 1)
+			{
+				RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
+				reduce_or_wire->name = NEW_ID;
+				module->wires[reduce_or_wire->name] = reduce_or_wire;
+
+				RTLIL::Cell *reduce_or_cell = new RTLIL::Cell;
+				reduce_or_cell->name = NEW_ID;
+				reduce_or_cell->type = "$reduce_or";
+				reduce_or_cell->connections["\\A"] = this_s;
+				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.width);
+				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+				module->cells[reduce_or_cell->name] = reduce_or_cell;
+
+				this_s = RTLIL::SigSpec(reduce_or_wire);
+				reduce_or_cell->connections["\\Y"] = this_s;
+			}
+
+			new_sig_b.append(this_b);
+			new_sig_s.append(this_s);
+			handled_sig.insert(this_b);
+		}
+
+		if (new_sig_s.width != sig_s.width) {
+			log("    New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
+			did_something = true;
+			OPT_DID_SOMETHING = true;
+			total_count++;
+		}
+
+		if (new_sig_s.width == 0)
+		{
+			module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
+			assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
+			module->cells.erase(cell->name);
+			delete cell;
+		}
+		else
+		{
+			cell->connections["\\B"] = new_sig_b;
+			cell->connections["\\S"] = new_sig_s;
+			if (new_sig_s.width > 1) {
+				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
+			} else {
+				cell->type = "$mux";
+				cell->parameters.erase("\\S_WIDTH");
+			}
+		}
+	}
+
+	OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module) :
+			design(design), module(module), assign_map(module)
+	{
+		log("  Optimizing cells in module %s.\n", module->name.c_str());
+
+		total_count = 0;
+		did_something = true;
+
+		while (did_something)
+		{
+			did_something = false;
+
+			// merge trees of reduce_* cells to one single cell and unify input vectors
+			// (only handle recduce_and and reduce_or for various reasons)
+
+			const char *type_list[] = { "$reduce_or", "$reduce_and" };
+			for (auto type : type_list)
+			{
+				SigSet<RTLIL::Cell*> drivers;
+				std::set<RTLIL::Cell*> cells;
+
+				for (auto &cell_it : module->cells) {
+					RTLIL::Cell *cell = cell_it.second;
+					if (cell->type != type || !design->selected(module, cell))
+						continue;
+					drivers.insert(assign_map(cell->connections["\\Y"]), cell);
+					cells.insert(cell);
+				}
+
+				while (cells.size() > 0) {
+					RTLIL::Cell *cell = *cells.begin();
+					opt_reduce(cells, drivers, cell);
+				}
+			}
+
+			// merge identical inputs on $mux and $pmux cells
+
+			for (auto &cell_it : module->cells)
+			{
+				RTLIL::Cell *cell = cell_it.second;
+				if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || !design->selected(module, cell))
+					continue;
+				opt_mux(cell);
+			}
+		}
+	}
+};
+
+struct OptReducePass : public Pass {
+	OptReducePass() : Pass("opt_reduce") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
+		extra_args(args, 1, design);
+
+		int total_count = 0;
+		for (auto &mod_it : design->modules) {
+			if (!design->selected(mod_it.second))
+				continue;
+			OptReduceWorker worker(design, mod_it.second);
+			total_count += worker.total_count;
+		}
+
+		log("Performed a total of %d changes.\n", total_count);
+	}
+} OptReducePass;
+ 
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
new file mode 100644
index 000000000..384a4d85f
--- /dev/null
+++ b/passes/opt/opt_rmdff.cc
@@ -0,0 +1,135 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+static SigMap assign_map;
+
+static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
+{
+	RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
+	RTLIL::Const val_cp, val_rp, val_rv;
+
+	if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
+		sig_d = dff->connections["\\D"];
+		sig_q = dff->connections["\\Q"];
+		sig_c = dff->connections["\\C"];
+		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
+	}
+	else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
+			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
+			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
+			(dff->type[8] == '0' || dff->type[8] == '1')) {
+		sig_d = dff->connections["\\D"];
+		sig_q = dff->connections["\\Q"];
+		sig_c = dff->connections["\\C"];
+		sig_r = dff->connections["\\R"];
+		val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
+		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
+		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
+	}
+	else if (dff->type == "$dff") {
+		sig_d = dff->connections["\\D"];
+		sig_q = dff->connections["\\Q"];
+		sig_c = dff->connections["\\CLK"];
+		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
+	}
+	else if (dff->type == "$adff") {
+		sig_d = dff->connections["\\D"];
+		sig_q = dff->connections["\\Q"];
+		sig_c = dff->connections["\\CLK"];
+		sig_r = dff->connections["\\ARST"];
+		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
+		val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
+		val_rv = dff->parameters["\\ARST_VALUE"];
+	}
+	else
+		log_error("abort.");
+	
+	assign_map.apply(sig_d);
+	assign_map.apply(sig_q);
+	assign_map.apply(sig_c);
+	assign_map.apply(sig_r);
+
+	if (sig_d.is_fully_const() && sig_r.width == 0) {
+		RTLIL::SigSig conn(sig_q, sig_d);
+		mod->connections.push_back(conn);
+		goto delete_dff;
+	}
+
+	if (sig_d == sig_q && sig_r.width == 0) {
+		goto delete_dff;
+	}
+
+	return false;
+
+delete_dff:
+	log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str());
+	OPT_DID_SOMETHING = true;
+	mod->cells.erase(dff->name);
+	delete dff;
+	return true;
+}
+
+struct OptRmdffPass : public Pass {
+	OptRmdffPass() : Pass("opt_rmdff") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		int total_count = 0;
+		log_header("Executing OPT_RMDFF pass (remove dff with constant values).\n");
+
+		extra_args(args, 1, design);
+
+		for (auto &mod_it : design->modules)
+		{
+			assign_map.set(mod_it.second);
+
+			std::vector<std::string> dff_list;
+			for (auto &it : mod_it.second->cells) {
+				if (it.second->type == "$_DFF_N_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_P_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_NN0_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_NN1_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_NP0_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_NP1_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_PN0_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_PN1_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_PP0_") dff_list.push_back(it.first);
+				if (it.second->type == "$_DFF_PP1_") dff_list.push_back(it.first);
+				if (it.second->type == "$dff") dff_list.push_back(it.first);
+				if (it.second->type == "$adff") dff_list.push_back(it.first);
+			}
+
+			for (auto &id : dff_list) {
+				if (mod_it.second->cells.count(id) > 0 &&
+						handle_dff(mod_it.second, mod_it.second->cells[id]))
+					total_count++;
+			}
+		}
+
+		assign_map.clear();
+		log("Replaced %d DFF cells.\n", total_count);
+	}
+} OptRmdffPass;
+ 
diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc
new file mode 100644
index 000000000..29a6f2bc4
--- /dev/null
+++ b/passes/opt/opt_rmunused.cc
@@ -0,0 +1,239 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include "kernel/celltypes.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <stdio.h>
+#include <set>
+
+static CellTypes ct;
+
+static void rmunused_module_cells(RTLIL::Module *module)
+{
+	SigMap assign_map(module);
+	std::set<RTLIL::Cell*> queue, unused;
+
+	SigSet<RTLIL::Cell*> wire2driver;
+	for (auto &it : module->cells) {
+		RTLIL::Cell *cell = it.second;
+		for (auto &it2 : cell->connections) {
+			if (!ct.cell_input(cell->type, it2.first)) {
+				RTLIL::SigSpec sig = it2.second;
+				assign_map.apply(sig);
+				wire2driver.insert(sig, cell);
+			}
+		}
+		if (cell->type == "$memwr")
+			queue.insert(cell);
+		unused.insert(cell);
+	}
+
+	for (auto &it : module->wires) {
+		RTLIL::Wire *wire = it.second;
+		if (wire->port_output) {
+			std::set<RTLIL::Cell*> cell_list;
+			RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
+			assign_map.apply(sig);
+			wire2driver.find(sig, cell_list);
+			for (auto cell : cell_list)
+				queue.insert(cell);
+		}
+	}
+
+	while (queue.size() > 0)
+	{
+		std::set<RTLIL::Cell*> new_queue;
+		for (auto cell : queue)
+			unused.erase(cell);
+		for (auto cell : queue) {
+			for (auto &it : cell->connections) {
+				if (!ct.cell_output(cell->type, it.first)) {
+					std::set<RTLIL::Cell*> cell_list;
+					RTLIL::SigSpec sig = it.second;
+					assign_map.apply(sig);
+					wire2driver.find(sig, cell_list);
+					for (auto cell : cell_list) {
+						if (unused.count(cell) > 0)
+							new_queue.insert(cell);
+					}
+				}
+			}
+		}
+		queue.swap(new_queue);
+	}
+
+	for (auto cell : unused) {
+		log("  removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
+		OPT_DID_SOMETHING = true;
+		module->cells.erase(cell->name);
+		delete cell;
+	}
+}
+
+static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
+{
+	assert(s1.width == 1);
+	assert(s2.width == 1);
+	assert(s1.chunks.size() == 1);
+	assert(s2.chunks.size() == 1);
+
+	RTLIL::Wire *w1 = s1.chunks[0].wire;
+	RTLIL::Wire *w2 = s2.chunks[0].wire;
+
+	if (w1 == NULL || w2 == NULL)
+		return w2 == NULL;
+
+	if (w1->port_input != w2->port_input)
+		return w2->port_input;
+
+	if (w1->name[0] != w2->name[0])
+		return w2->name[0] == '\\';
+
+	if (w1->attributes.size() != w2->attributes.size())
+		return w2->attributes.size() > w1->attributes.size();
+
+	return w2->name < w1->name;
+}
+
+static void rmunused_module_signals(RTLIL::Module *module)
+{
+	SigMap assign_map(module);
+	for (auto &it : module->wires) {
+		RTLIL::Wire *wire = it.second;
+		for (int i = 0; i < wire->width; i++) {
+			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
+			if (!compare_signals(s1, s2))
+				assign_map.add(s1);
+		}
+	}
+
+	module->connections.clear();
+
+	SigPool used_signals;
+	SigPool used_signals_nodrivers;
+	for (auto &it : module->cells) {
+		RTLIL::Cell *cell = it.second;
+		for (auto &it2 : cell->connections) {
+			assign_map.apply(it2.second);
+			used_signals.add(it2.second);
+			if (!ct.cell_output(cell->type, it2.first))
+				used_signals_nodrivers.add(it2.second);
+		}
+	}
+
+	std::vector<RTLIL::Wire*> del_wires;
+	for (auto &it : module->wires) {
+		RTLIL::Wire *wire = it.second;
+		if (wire->name[0] == '\\') {
+			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
+			assign_map.apply(s2);
+			if (!used_signals.check_any(s2) && wire->port_id == 0) {
+				log("  removing unused non-port wire %s.\n", wire->name.c_str());
+				del_wires.push_back(wire);
+			} else {
+				s1.expand();
+				s2.expand();
+				assert(s1.chunks.size() == s2.chunks.size());
+				RTLIL::SigSig new_conn;
+				for (size_t i = 0; i < s1.chunks.size(); i++)
+					if (s1.chunks[i] != s2.chunks[i]) {
+						new_conn.first.append(s1.chunks[i]);
+						new_conn.second.append(s2.chunks[i]);
+					}
+				if (new_conn.first.width > 0) {
+					new_conn.first.optimize();
+					new_conn.second.optimize();
+					module->connections.push_back(new_conn);
+				}
+			}
+		} else {
+			if (!used_signals.check_any(RTLIL::SigSpec(wire)))
+				del_wires.push_back(wire);
+		}
+		RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
+		if (!used_signals_nodrivers.check_any(sig)) {
+			std::string unused_bits;
+			sig.expand();
+			for (size_t i = 0; i < sig.chunks.size(); i++) {
+				if (sig.chunks[i].wire == NULL)
+					continue;
+				if (!used_signals_nodrivers.check_any(sig)) {
+					if (!unused_bits.empty())
+						unused_bits += " ";
+					unused_bits += stringf("%zd", i);
+				}
+			}
+			if (unused_bits.empty() || wire->port_id != 0)
+				wire->attributes.erase("\\unused_bits");
+			else
+				wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
+		} else {
+			wire->attributes.erase("\\unused_bits");
+		}
+	}
+
+	for (auto wire : del_wires) {
+		module->wires.erase(wire->name);
+		delete wire;
+	}
+
+	if (del_wires.size() > 0)
+		log("  removed %zd unused temporary wires.\n", del_wires.size());
+}
+
+static void rmunused_module(RTLIL::Module *module)
+{
+	log("Finding unused cells or wires in module %s..\n", module->name.c_str());
+
+	rmunused_module_cells(module);
+	rmunused_module_signals(module);
+}
+
+struct OptRmUnusedPass : public Pass {
+	OptRmUnusedPass() : Pass("opt_rmunused") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT_RMUNUSED pass (remove unused cells and wires).\n");
+		log_push();
+
+		extra_args(args, 1, design);
+
+		ct.setup_internals();
+		ct.setup_internals_mem();
+		ct.setup_stdcells();
+		ct.setup_stdcells_mem();
+
+		for (auto &mod_it : design->modules) {
+			if (mod_it.second->processes.size() > 0) {
+				log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+			} else {
+				rmunused_module(mod_it.second);
+			}
+		}
+
+		ct.clear();
+		log_pop();
+	}
+} OptRmUnusedPass;
+ 
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
new file mode 100644
index 000000000..ecad8b436
--- /dev/null
+++ b/passes/opt/opt_share.cc
@@ -0,0 +1,250 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "opt_status.h"
+#include "kernel/register.h"
+#include "kernel/sigtools.h"
+#include "kernel/log.h"
+#include "kernel/sha1.h"
+#include "kernel/celltypes.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <stdio.h>
+#include <set>
+
+#define USE_CELL_HASH_CACHE
+
+struct OptShareWorker
+{
+	RTLIL::Design *design;
+	RTLIL::Module *module;
+	SigMap assign_map;
+
+	CellTypes ct;
+	int total_count;
+#ifdef USE_CELL_HASH_CACHE
+	std::map<const RTLIL::Cell*, std::string> cell_hash_cache;
+#endif
+
+#ifdef USE_CELL_HASH_CACHE
+	std::string int_to_hash_string(unsigned int v)
+	{
+		if (v == 0)
+			return "0";
+		std::string str = "";
+		while (v > 0) {
+			str += 'a' + (v & 15);
+			v = v >> 4;
+		}
+		return str;
+	}
+
+	std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
+	{
+		if (cell_hash_cache.count(cell) > 0)
+			return cell_hash_cache[cell];
+
+		std::string hash_string = cell->type + "\n";
+
+		for (auto &it : cell->parameters)
+			hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
+
+		for (auto &it : cell->connections) {
+			if (ct.cell_output(cell->type, it.first))
+				continue;
+			RTLIL::SigSpec sig = it.second;
+			assign_map.apply(sig);
+			hash_string += "C " + it.first + "=";
+			for (auto &chunk : sig.chunks) {
+				if (chunk.wire)
+					hash_string += "{" + chunk.wire->name + " " +
+							int_to_hash_string(chunk.offset) + " " +
+							int_to_hash_string(chunk.width) + "}";
+				else
+					hash_string += chunk.data.as_string();
+			}
+			hash_string += "\n";
+		}
+
+		unsigned char hash[20];
+		char hash_hex_string[41];
+		sha1::calc(hash_string.c_str(), hash_string.size(), hash);
+		sha1::toHexString(hash, hash_hex_string);
+		cell_hash_cache[cell] = hash_hex_string;
+
+		return cell_hash_cache[cell];
+	}
+#endif
+
+	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool &lt)
+	{
+#ifdef USE_CELL_HASH_CACHE
+		std::string hash1 = hash_cell_parameters_and_connections(cell1);
+		std::string hash2 = hash_cell_parameters_and_connections(cell2);
+
+		if (hash1 != hash2) {
+			lt = hash1 < hash2;
+			return true;
+		}
+#endif
+
+		if (cell1->parameters != cell2->parameters) {
+			lt = cell1->parameters < cell2->parameters;
+			return true;
+		}
+
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections;
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections;
+
+		for (auto &it : conn1) {
+			if (ct.cell_output(cell1->type, it.first))
+				it.second = RTLIL::SigSpec();
+			else
+				assign_map.apply(it.second);
+		}
+
+		for (auto &it : conn2) {
+			if (ct.cell_output(cell2->type, it.first))
+				it.second = RTLIL::SigSpec();
+			else
+				assign_map.apply(it.second);
+		}
+
+		if (conn1 != conn2) {
+			lt = conn1 < conn2;
+			return true;
+		}
+
+		return false;
+	}
+
+	bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
+	{
+		if (cell1->type != cell2->type)
+			return cell1->type < cell2->type;
+
+		if (!ct.cell_known(cell1->type))
+			return cell1 < cell2;
+
+		bool lt;
+		if (compare_cell_parameters_and_connections(cell1, cell2, lt))
+			return lt;
+
+		return false;
+	}
+
+	struct CompareCells {
+		OptShareWorker *that;
+		CompareCells(OptShareWorker *that) : that(that) {}
+		bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
+			return that->compare_cells(cell1, cell2);
+		}
+	};
+
+	OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux) :
+		design(design), module(module), assign_map(module)
+	{
+		total_count = 0;
+		ct.setup_internals();
+		ct.setup_internals_mem();
+		ct.setup_stdcells();
+		ct.setup_stdcells_mem();
+
+		if (mode_nomux) {
+			ct.cell_types.erase("$mux");
+			ct.cell_types.erase("$pmux");
+			ct.cell_types.erase("$safe_pmux");
+		}
+
+		log("Finding identical cells in module `%s'.\n", module->name.c_str());
+		assign_map.set(module);
+
+		bool did_something = true;
+		while (did_something)
+		{
+#ifdef USE_CELL_HASH_CACHE
+			cell_hash_cache.clear();
+#endif
+			std::vector<RTLIL::Cell*> cells;
+			cells.reserve(module->cells.size());
+			for (auto &it : module->cells) {
+				if (ct.cell_known(it.second->type) && design->selected(module, it.second))
+					cells.push_back(it.second);
+			}
+
+			did_something = false;
+			std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
+			for (auto cell : cells)
+			{
+				if (sharemap.count(cell) > 0) {
+					did_something = true;
+					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
+					for (auto &it : cell->connections) {
+						if (ct.cell_output(cell->type, it.first)) {
+							RTLIL::SigSpec other_sig = sharemap[cell]->connections[it.first];
+							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
+									log_signal(it.second), log_signal(other_sig));
+							module->connections.push_back(RTLIL::SigSig(it.second, other_sig));
+							assign_map.add(it.second, other_sig);
+						}
+					}
+					log("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+					module->cells.erase(cell->name);
+					OPT_DID_SOMETHING = true;
+					total_count++;
+					delete cell;
+				} else {
+					sharemap[cell] = cell;
+				}
+			}
+		}
+	}
+};
+
+struct OptSharePass : public Pass {
+	OptSharePass() : Pass("opt_share") { }
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header("Executing OPT_SHARE pass (detect identical cells).\n");
+
+		bool mode_nomux = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-nomux") {
+				mode_nomux = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		int total_count = 0;
+		for (auto &mod_it : design->modules) {
+			if (!design->selected(mod_it.second))
+				continue;
+			OptShareWorker worker(design, mod_it.second, mode_nomux);
+			total_count += worker.total_count;
+		}
+
+		log("Removed a total of %d cells.\n", total_count);
+	}
+} OptSharePass;
+ 
diff --git a/passes/opt/opt_status.h b/passes/opt/opt_status.h
new file mode 100644
index 000000000..3d12baa7d
--- /dev/null
+++ b/passes/opt/opt_status.h
@@ -0,0 +1,26 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef OPT_STATUS_H
+#define OPT_STATUS_H
+
+extern bool OPT_DID_SOMETHING;
+
+#endif
+