Refactoring: Renamed RTLIL::Module::wires to wires_

5 files changed, 9 insertions, 9 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 63d03b205..9542e10df 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -52,7 +52,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 		unused.insert(cell);
 	}
 
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
 		if (wire->port_output || wire->get_bool_attribute("\\keep")) {
 			std::set<RTLIL::Cell*> cell_list;
@@ -175,12 +175,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 				if (ct_all.cell_output(cell->type, it2.first))
 					direct_sigs.insert(assign_map(it2.second));
 	}
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
 			direct_wires.insert(it.second);
 	}
 
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
 		for (int i = 0; i < wire->width; i++) {
 			RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
@@ -202,7 +202,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 				used_signals_nodrivers.add(it2.second);
 		}
 	}
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
 		if (wire->port_id > 0) {
 			RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
@@ -219,7 +219,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 	}
 
 	std::vector<RTLIL::Wire*> maybe_del_wires;
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		RTLIL::Wire *wire = it.second;
 		if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) {
 			RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 672186006..290d4ffd9 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -45,7 +45,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 			used_signals.add(sigmap(conn.second));
 	}
 
-	for (auto &it : module->wires) {
+	for (auto &it : module->wires_) {
 		if (it.second->port_input)
 			driven_signals.add(sigmap(it.second));
 		if (it.second->port_output)
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 8487152ff..16dedef58 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -136,7 +136,7 @@ struct OptMuxtreeWorker
 				}
 			}
 		}
-		for (auto &it : module->wires) {
+		for (auto &it : module->wires_) {
 			if (it.second->port_output)
 				for (int idx : sig2bits(RTLIL::SigSpec(it.second)))
 					bit2info[idx].seen_non_mux = true;
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 8c09f5414..b26e8b37e 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -173,7 +173,7 @@ struct OptRmdffPass : public Pass {
 
 			assign_map.set(mod_it.second);
 			dff_init_map.set(mod_it.second);
-			for (auto &it : mod_it.second->wires)
+			for (auto &it : mod_it.second->wires_)
 				if (it.second->attributes.count("\\init") != 0)
 					dff_init_map.add(it.second, it.second->attributes.at("\\init"));
 			mux_drivers.clear();
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 4f733a373..c91f037d4 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -237,7 +237,7 @@ struct OptShareWorker
 		assign_map.set(module);
 
 		dff_init_map.set(module);
-		for (auto &it : module->wires)
+		for (auto &it : module->wires_)
 			if (it.second->attributes.count("\\init") != 0)
 				dff_init_map.add(it.second, it.second->attributes.at("\\init"));