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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-14 10:22:33 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-14 10:22:33 -0700 |
commit | aad97168b070509b7bd479ed3b9956452a28e3ec (patch) | |
tree | 8d3bc9b495f895d96ff539c119f409ea13a18ea0 /passes/pmgen/ice40_dsp.cc | |
parent | 2f04beeeb5114058ce762d0393859d517a9a35eb (diff) | |
download | yosys-aad97168b070509b7bd479ed3b9956452a28e3ec.tar.gz yosys-aad97168b070509b7bd479ed3b9956452a28e3ec.tar.bz2 yosys-aad97168b070509b7bd479ed3b9956452a28e3ec.zip |
Fixes for reverting SigSpec helper functions
Diffstat (limited to 'passes/pmgen/ice40_dsp.cc')
-rw-r--r-- | passes/pmgen/ice40_dsp.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 66f70399d..6f0539679 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -155,9 +155,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // If we have a signed multiply-add, then perform sign extension // TODO: Need to check CD[31:16] is sign extension of CD[15:0]? if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool()) - pm.module->connect(O[-1], O[-2]); + pm.module->connect(O[32], O[31]); else - cell->setPort("\\CO", O[-1]); + cell->setPort("\\CO", O[32]); O.remove(O_width-1); } else |