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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 15:35:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 15:35:48 +0100 |
| commit | 5a853ed46cd3a41df9da4c8206f9416748788487 (patch) | |
| tree | 60eef6d0bc328c18733f69a508c1b24c26bca5c8 /passes/pmgen/ice40_dsp.pmg | |
| parent | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (diff) | |
| download | yosys-5a853ed46cd3a41df9da4c8206f9416748788487.tar.gz yosys-5a853ed46cd3a41df9da4c8206f9416748788487.tar.bz2 yosys-5a853ed46cd3a41df9da4c8206f9416748788487.zip | |
Add actual DSP inference to ice40_dsp pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 1370cb66a..58e1ce0e0 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -63,7 +63,7 @@ code sigY clock clock_pol clock_vld sigY = port(mul, \Y); if (ffY) { - sigY = port(ffY, \D); + sigY = port(ffY, \Q); SigBit c = port(ffY, \CLK).as_bit(); bool cp = param(ffY, \CLK_POLARITY).as_bool(); @@ -77,7 +77,7 @@ code sigY clock clock_pol clock_vld endcode match addA - select addA->type.in($add, $sub) + select addA->type.in($add) select nusers(port(addA, \A)) == 2 index <SigSpec> port(addA, \A) === sigY optional @@ -134,3 +134,17 @@ match ffS index <SigSpec> port(ffS, \D) === port(muxAB, \Y) index <SigSpec> port(ffS, \Q) === sigS endmatch + +code clock clock_pol clock_vld + if (ffS) { + SigBit c = port(ffS, \CLK).as_bit(); + bool cp = param(ffS, \CLK_POLARITY).as_bool(); + + if (clock_vld && (c != clock || cp != clock_pol)) + reject; + + clock = c; + clock_pol = cp; + clock_vld = true; + } +endcode |