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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-29 13:02:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-29 13:02:05 +0200 |
| commit | 9f792c599db0cc466444d58e3c675711deb6349b (patch) | |
| tree | 483be9da99afb9b62e98bccc672f02a63f6dac9a /passes/pmgen/ice40_dsp.pmg | |
| parent | 32881a989c2eb2cc73e224e6dc20dc3949f90e55 (diff) | |
| download | yosys-9f792c599db0cc466444d58e3c675711deb6349b.tar.gz yosys-9f792c599db0cc466444d58e3c675711deb6349b.tar.bz2 yosys-9f792c599db0cc466444d58e3c675711deb6349b.zip | |
Add pmgen support for multiple patterns in one matcher
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 96c62e313..1f3590d4e 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,3 +1,5 @@ +pattern ice40_dsp + state <SigBit> clock state <bool> clock_pol clock_vld state <SigSpec> sigA sigB sigY sigS |