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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-20 11:18:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-20 11:18:19 +0100 |
| commit | dca65d83a0037539464d303ea8751a3e06a92e03 (patch) | |
| tree | 6609dce7db4f254131e7e0cefa1aefa5e7c9d64d /passes/pmgen/ice40_dsp.pmg | |
| parent | 62493c91b24c1775f82e64712bf42b175944fe08 (diff) | |
| download | yosys-dca65d83a0037539464d303ea8751a3e06a92e03.tar.gz yosys-dca65d83a0037539464d303ea8751a3e06a92e03.tar.bz2 yosys-dca65d83a0037539464d303ea8751a3e06a92e03.zip | |
Detect and reject cases that do not map well to iCE40 DSPs (yet)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 58e1ce0e0..96c62e313 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -100,6 +100,16 @@ code addAB sigS addAB = addB; sigS = port(addB, \A); } + if (addAB) { + int natural_mul_width = GetSize(sigA) + GetSize(sigB); + int actual_mul_width = GetSize(sigY); + int actual_acc_width = GetSize(sigS); + + if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) + reject; + if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) + reject; + } endcode match muxA |