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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 11:55:51 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-28 11:55:51 -0800 |
| commit | 7939727d14f44b5d56ca3806d0907e9fceea2882 (patch) | |
| tree | 8237e2063e8e8b39bf0b8142c82a447f9c7ae3d6 /passes/pmgen/ice40_wrapcarry.cc | |
| parent | 245b8c4ab64c5c3bd7b9f71f94316a76a2576fd1 (diff) | |
| parent | 6d27d4372730cb94306a4f314482459f9d527d7c (diff) | |
| download | yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.tar.gz yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.tar.bz2 yosys-7939727d14f44b5d56ca3806d0907e9fceea2882.zip | |
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
Diffstat (limited to 'passes/pmgen/ice40_wrapcarry.cc')
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index d458dce46..0053c8872 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -127,7 +127,7 @@ struct Ice40WrapCarryPass : public Pass { lut->setParam(ID(WIDTH), 4); lut->setParam(ID(LUT), cell->getParam(ID(LUT))); auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 }); + lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) }); lut->setPort(ID(Y), cell->getPort(ID(O))); Const src; |