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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 10:46:33 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 10:46:33 -0700 |
commit | 05282afc2503d1dba1da561c7fbf86ac6cf97466 (patch) | |
tree | 4cc580877bc94217dfb1069c82e4bada4bfa8f3b /passes/pmgen/xilinx_dsp.cc | |
parent | 0166e02e781080f346b37dcb3ba6f9fa947ca22d (diff) | |
download | yosys-05282afc2503d1dba1da561c7fbf86ac6cf97466.tar.gz yosys-05282afc2503d1dba1da561c7fbf86ac6cf97466.tar.bz2 yosys-05282afc2503d1dba1da561c7fbf86ac6cf97466.zip |
Add support for CEB, remove check on nusers
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
-rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 2f36a5bde..5ae34a1f7 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -34,6 +34,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("ffA: %s\n", log_id(st.ffA, "--")); log("ffAmux: %s\n", log_id(st.ffAmux, "--")); log("ffB: %s\n", log_id(st.ffB, "--")); + log("ffBmux: %s\n", log_id(st.ffBmux, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); log("ffMmux: %s\n", log_id(st.ffMmux, "--")); @@ -81,8 +82,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) SigSpec D = st.ffA->getPort("\\D"); SigSpec Q = pm.sigmap(st.ffA->getPort("\\Q")); A.replace(Q, D); - - cell->setParam("\\AREG", 1); if (st.ffAmux) { SigSpec Y = st.ffAmux->getPort("\\Y"); SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A"); @@ -92,19 +91,25 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) else cell->setPort("\\CEA2", State::S1); cell->setPort("\\A", A); + + cell->setParam("\\AREG", 1); } if (st.ffB) { SigSpec B = cell->getPort("\\B"); SigSpec D = st.ffB->getPort("\\D"); SigSpec Q = st.ffB->getPort("\\Q"); B.replace(Q, D); + if (st.ffBmux) { + SigSpec Y = st.ffBmux->getPort("\\Y"); + SigSpec AB = st.ffBmux->getPort(st.ffBmuxAB == "\\A" ? "\\B" : "\\A"); + B.replace(Y, AB); + cell->setPort("\\CEB2", st.ffBmux->getPort("\\S")); + } + else + cell->setPort("\\CEB2", State::S1); cell->setPort("\\B", B); + cell->setParam("\\BREG", 1); - if (st.ffB->type == "$dff") - cell->setPort("\\CEB2", State::S1); - //else if (st.ffB->type == "$dffe") - // cell->setPort("\\CEB2", st.ffB->getPort("\\EN")); - else log_abort(); } if (st.ffM) { SigSpec D = st.ffM->getPort("\\D"); |