diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:24:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 16:24:59 -0700 |
| commit | 16316aa05d548c79fa1580defe71097efdeb78b9 (patch) | |
| tree | fa4e2d6da0791b4e06b714ccfde59f09946de090 /passes/pmgen/xilinx_dsp.cc | |
| parent | cd002ad3fb20bb98027f29e0c1005bf1df7c432c (diff) | |
| download | yosys-16316aa05d548c79fa1580defe71097efdeb78b9.tar.gz yosys-16316aa05d548c79fa1580defe71097efdeb78b9.tar.bz2 yosys-16316aa05d548c79fa1580defe71097efdeb78b9.zip | |
Rename muxAB to postAddMux
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 7f51d29f6..17e05c39c 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -35,15 +35,15 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) #if 1 log("\n"); - log("ffA: %s\n", log_id(st.ffA, "--")); - log("ffB: %s\n", log_id(st.ffB, "--")); - log("dsp: %s\n", log_id(st.dsp, "--")); - log("ffM: %s\n", log_id(st.ffM, "--")); - log("postAdd: %s\n", log_id(st.postAdd, "--")); - log("muxAB: %s\n", log_id(st.muxAB, "--")); - log("ffP: %s\n", log_id(st.ffP, "--")); + log("ffA: %s\n", log_id(st.ffA, "--")); + log("ffB: %s\n", log_id(st.ffB, "--")); + log("dsp: %s\n", log_id(st.dsp, "--")); + log("ffM: %s\n", log_id(st.ffM, "--")); + log("postAdd: %s\n", log_id(st.postAdd, "--")); + log("postAddMux: %s\n", log_id(st.postAddMux, "--")); + log("ffP: %s\n", log_id(st.ffP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--")); - log("sigPused: %s\n", log_signal(st.sigPused)); + log("sigPused: %s\n", log_signal(st.sigPused)); #endif log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp)); @@ -59,9 +59,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); SigSpec &opmode = cell->connections_.at("\\OPMODE"); - if (st.ffP && st.muxAB) { - opmode[4] = st.muxAB->getPort("\\S"); - pm.autoremove(st.muxAB); + if (st.ffP && st.postAddMux) { + opmode[4] = st.postAddMux->getPort("\\S"); + pm.autoremove(st.postAddMux); } else if (st.ffP && C == P) { C = SigSpec(); |