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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 21:38:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 21:38:35 -0700 |
| commit | 174edbcb96f780592cde1952db6ee7e58e8e2f56 (patch) | |
| tree | dd223cb2c1bcc622f1891b54fa7aabaadcd263ee /passes/pmgen/xilinx_dsp.cc | |
| parent | 53ca536d674ade382da16adddfb02db7e970acef (diff) | |
| download | yosys-174edbcb96f780592cde1952db6ee7e58e8e2f56.tar.gz yosys-174edbcb96f780592cde1952db6ee7e58e8e2f56.tar.bz2 yosys-174edbcb96f780592cde1952db6ee7e58e8e2f56.zip | |
Sensitive to CEB CEM CEP polarity
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 16a098fd0..38b1a12be 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -84,8 +84,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) if (st.ffAmux) { SigSpec Y = st.ffAmux->getPort("\\Y"); SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B"); - A.replace(Y, AB); SigSpec S = st.ffAmux->getPort("\\S"); + A.replace(Y, AB); cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S)); } else @@ -101,9 +101,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) B.replace(Q, D); if (st.ffBmux) { SigSpec Y = st.ffBmux->getPort("\\Y"); - SigSpec AB = st.ffBmux->getPort(st.ffBmuxAB == "\\A" ? "\\B" : "\\A"); + SigSpec AB = st.ffBmux->getPort(st.ffBenpol ? "\\A" : "\\B"); + SigSpec S = st.ffBmux->getPort("\\S"); B.replace(Y, AB); - cell->setPort("\\CEB2", st.ffBmux->getPort("\\S")); + cell->setPort("\\CEB2", st.ffBenpol ? S : pm.module->Not(NEW_ID, S)); } else cell->setPort("\\CEB2", State::S1); @@ -113,7 +114,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) } if (st.ffM) { if (st.ffMmux) { - cell->setPort("\\CEM", st.ffMmux->getPort("\\S")); + SigSpec S = st.ffMmux->getPort("\\S"); + cell->setPort("\\CEM", st.ffMenpol ? S : pm.module->Not(NEW_ID, S)); pm.autoremove(st.ffMmux); } else @@ -127,7 +129,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) } if (st.ffP) { if (st.ffPmux) { - cell->setPort("\\CEP", st.ffPmux->getPort("\\S")); + SigSpec S = st.ffPmux->getPort("\\S"); + cell->setPort("\\CEP", st.ffPenpol ? S : pm.module->Not(NEW_ID, S)); st.ffPmux->connections_.at("\\Y").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); } else |