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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:21:24 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-13 10:21:24 -0700 |
commit | 2a1b98d478918b0a17c7e509ada6e7a71bbab526 (patch) | |
tree | 08db51f86e8ee1ebac897e7fb4a4e23ee1503f6f /passes/pmgen/xilinx_dsp.cc | |
parent | f890cfb63b71ae7b09e19c290ec70c358dcbe9cd (diff) | |
download | yosys-2a1b98d478918b0a17c7e509ada6e7a71bbab526.tar.gz yosys-2a1b98d478918b0a17c7e509ada6e7a71bbab526.tar.bz2 yosys-2a1b98d478918b0a17c7e509ada6e7a71bbab526.zip |
Add DSP_A_MAXWIDTH_PARTIAL, refactor
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
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