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| author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:11 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2020-02-03 10:56:41 -0300 |
| commit | 313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc (patch) | |
| tree | f35f8834f0cc30380c32d5ed3a38cb2673304931 /passes/pmgen/xilinx_dsp.cc | |
| parent | 71f3afb9a26e7bad2a9e9d59877a94cbd757cad4 (diff) | |
| parent | 7033503cd9e40e16c11fe6c805a436b0e23989dd (diff) | |
| download | yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.gz yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.tar.bz2 yosys-313a425bd58f1bf0f7f48d86cf0a42a88a93c5dc.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 81c3c57c4..ae7967d7c 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass { log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n"); log("device.\n"); log("\n"); + log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n"); + log("to 1.\n"); + log("\n"); log("\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n"); @@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass { family = "xcu"; for (auto module : design->selected_modules()) { + + if (design->scratchpad_get_bool("xilinx_dsp.multonly")) + continue; + // Experimental feature: pack $add/$sub cells with // (* use_dsp48="simd" *) into DSP48E1's using its // SIMD feature |