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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 14:57:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 14:57:59 -0700 |
| commit | 682153de4bb1869187e567a41c22fbed23bcdfd1 (patch) | |
| tree | f6f87f8c7b79d7b4985a7e199ce41c855dcf0a4a /passes/pmgen/xilinx_dsp.cc | |
| parent | 97d11708e0104f722578b98ea70a0ba41f9e03cc (diff) | |
| download | yosys-682153de4bb1869187e567a41c22fbed23bcdfd1.tar.gz yosys-682153de4bb1869187e567a41c22fbed23bcdfd1.tar.bz2 yosys-682153de4bb1869187e567a41c22fbed23bcdfd1.zip | |
Process post-adder first since C could be used for load-P
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 40 |
1 files changed, 22 insertions, 18 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 9307b3d37..1732a2d6a 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -49,8 +49,27 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) Cell *cell = st.dsp; bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell)); + SigSpec C = st.sigC; SigSpec P = st.sigP; + if (st.addAB) { + log_assert(st.addAB->getParam("\\A_SIGNED").as_bool()); + log_assert(st.addAB->getParam("\\B_SIGNED").as_bool()); + log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); + + SigSpec &opmode = cell->connections_.at("\\OPMODE"); + if (st.ffP && C == P) { + C = SigSpec(); + opmode[4] = State::S0; + } + else + opmode[4] = State::S1; + opmode[6] = State::S0; + opmode[5] = State::S1; + + pm.autoremove(st.addAB); + } + if (st.clock != SigBit()) { cell->setPort("\\CLK", st.clock); @@ -125,25 +144,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("\n"); } - if (st.addAB) { - log_assert(st.addAB->getParam("\\A_SIGNED").as_bool()); - log_assert(st.addAB->getParam("\\B_SIGNED").as_bool()); - log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); - - SigSpec C = st.sigC; - SigSpec &opmode = cell->connections_.at("\\OPMODE"); - if (cell->getParam("\\PREG").as_bool() && C == P) { - opmode[4] = State::S0; - } - else { + if (!C.empty()) { + if (GetSize(C) < 48) C.extend_u0(48, true); - cell->setPort("\\C", C); - opmode[4] = State::S1; - } - opmode[6] = State::S0; - opmode[5] = State::S1; - - pm.autoremove(st.addAB); + cell->setPort("\\C", C); } if (GetSize(P) < 48) |