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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 14:36:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 14:36:10 -0700 |
| commit | 8246062acfd3b294c59ce72a9dcc6513dc0d08bd (patch) | |
| tree | 158b984e2b781734dc34b954af759886b8d08d3f /passes/pmgen/xilinx_dsp.cc | |
| parent | 2c32056990b9742839841f4cf3fa31d742cef472 (diff) | |
| download | yosys-8246062acfd3b294c59ce72a9dcc6513dc0d08bd.tar.gz yosys-8246062acfd3b294c59ce72a9dcc6513dc0d08bd.tar.bz2 yosys-8246062acfd3b294c59ce72a9dcc6513dc0d08bd.zip | |
Fix enable polarity
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 65a4d5a11..d8213e02f 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -112,7 +112,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) A.replace(Q, D); if (st.ffAmux) { SigSpec Y = st.ffAmux->getPort("\\Y"); - SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\A" : "\\B"); + SigSpec AB = st.ffAmux->getPort(st.ffAenpol ? "\\B" : "\\A"); SigSpec S = st.ffAmux->getPort("\\S"); A.replace(Y, AB); cell->setPort("\\CEA2", st.ffAenpol ? S : pm.module->Not(NEW_ID, S)); @@ -130,7 +130,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) B.replace(Q, D); if (st.ffBmux) { SigSpec Y = st.ffBmux->getPort("\\Y"); - SigSpec AB = st.ffBmux->getPort(st.ffBenpol ? "\\A" : "\\B"); + SigSpec AB = st.ffBmux->getPort(st.ffBenpol ? "\\B" : "\\A"); SigSpec S = st.ffBmux->getPort("\\S"); B.replace(Y, AB); cell->setPort("\\CEB2", st.ffBenpol ? S : pm.module->Not(NEW_ID, S)); |