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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:30:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:30:04 -0700 |
| commit | 8f503fe3e65ba9be2ef7438b2f4143f88ea8a025 (patch) | |
| tree | aab79bf524deb8cfbc3fd2f3a6212645ddc9267e /passes/pmgen/xilinx_dsp.cc | |
| parent | e67f049e3b1c1ed643b86b5237b31075d0f2f212 (diff) | |
| download | yosys-8f503fe3e65ba9be2ef7438b2f4143f88ea8a025.tar.gz yosys-8f503fe3e65ba9be2ef7438b2f4143f88ea8a025.tar.bz2 yosys-8f503fe3e65ba9be2ef7438b2f4143f88ea8a025.zip | |
autoremove ffM
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 50af5de1c..631b93afa 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -106,6 +106,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) //else if (st.ffP->type == "$dffe") // cell->setPort("\\CEM", st.ffM->getPort("\\EN")); else log_abort(); + pm.autoremove(st.ffM); } if (st.ffP) { SigSpec D; |