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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:45:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:45:25 -0700 |
| commit | 91629ee4b3aae3aa8243a659ffe1716ad5c432a2 (patch) | |
| tree | 98f0e293b418e04aadd0bcb427e8c23927357849 /passes/pmgen/xilinx_dsp.cc | |
| parent | 8dca8d486e945eb5883e6757f711011ed23aa5ba (diff) | |
| download | yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.tar.gz yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.tar.bz2 yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.zip | |
Pattern matcher to check pool of bits, not exactly
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index a4602dd63..bd04cc40b 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -49,8 +49,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) cell->setPort("\\CLK", st.clock); if (st.ffA) { + SigSpec A = cell->getPort("\\A"); SigSpec D = st.ffA->getPort("\\D"); - cell->setPort("\\A", D.extend_u0(30, true)); + SigSpec Q = st.ffA->getPort("\\Q"); + A.replace(Q, D); + cell->setPort("\\A", A); cell->setParam("\\AREG", State::S1); if (st.ffA->type == "$dff") cell->setPort("\\CEA2", State::S1); @@ -59,8 +62,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) else log_abort(); } if (st.ffB) { + SigSpec B = cell->getPort("\\B"); SigSpec D = st.ffB->getPort("\\D"); - cell->setPort("\\B", D.extend_u0(18, true)); + SigSpec Q = st.ffB->getPort("\\Q"); + B.replace(Q, D); + cell->setPort("\\B", B); cell->setParam("\\BREG", State::S1); if (st.ffB->type == "$dff") cell->setPort("\\CEB2", State::S1); @@ -71,7 +77,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) if (st.ffP) { SigSpec P = cell->getPort("\\P"); SigSpec Q = st.ffP->getPort("\\Q"); - Q.append(P.extract(GetSize(Q), -1)); + P.replace(Q, P.extract(0, GetSize(Q))); cell->setPort("\\P", Q); cell->setParam("\\PREG", State::S1); if (st.ffP->type == "$dff") |