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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:38:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 12:38:47 -0700 |
| commit | a32b14a55f888664981dc6b1184b00f34f5f4201 (patch) | |
| tree | 954fea09cfaa759533e12a920657a9cfa4220e86 /passes/pmgen/xilinx_dsp.cc | |
| parent | 7bd55f379ca3bf8f79c290e9851d14b20c1f5c28 (diff) | |
| download | yosys-a32b14a55f888664981dc6b1184b00f34f5f4201.tar.gz yosys-a32b14a55f888664981dc6b1184b00f34f5f4201.tar.bz2 yosys-a32b14a55f888664981dc6b1184b00f34f5f4201.zip | |
Do not check signedness of post-adder (assume taken care of by DSP)
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 6e82ffac3..9291c2dfb 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -52,8 +52,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) SigSpec P = st.sigP; if (st.postAdd) { - log_assert(st.postAdd->getParam("\\A_SIGNED").as_bool()); - log_assert(st.postAdd->getParam("\\B_SIGNED").as_bool()); log(" adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type)); SigSpec &opmode = cell->connections_.at("\\OPMODE"); |