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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
| commit | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (patch) | |
| tree | f1b284aebe30d0f7eabd9e8919b4275a38ff2ae4 /passes/pmgen/xilinx_dsp.cc | |
| parent | 5aaa19f1ab33394accbe633cd96a3fbe281dd09a (diff) | |
| parent | 5ebdc0f8e07989b79337ced0553bd28819a8cf3e (diff) | |
| download | yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.gz yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.bz2 yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.zip | |
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 81c3c57c4..ae7967d7c 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass { log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n"); log("device.\n"); log("\n"); + log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n"); + log("to 1.\n"); + log("\n"); log("\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n"); @@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass { family = "xcu"; for (auto module : design->selected_modules()) { + + if (design->scratchpad_get_bool("xilinx_dsp.multonly")) + continue; + // Experimental feature: pack $add/$sub cells with // (* use_dsp48="simd" *) into DSP48E1's using its // SIMD feature |