diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 22:06:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 22:06:23 -0700 |
| commit | cba63fe72b27c135e5fe04560d3a625e82c65fe3 (patch) | |
| tree | 752061c5f29dc28992bcfd96e2dea2c84f24664c /passes/pmgen/xilinx_dsp.cc | |
| parent | 1fc50a03fcaeebc0d1b12f397c2d31bcd27df715 (diff) | |
| download | yosys-cba63fe72b27c135e5fe04560d3a625e82c65fe3.tar.gz yosys-cba63fe72b27c135e5fe04560d3a625e82c65fe3.tar.bz2 yosys-cba63fe72b27c135e5fe04560d3a625e82c65fe3.zip | |
Oops
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 7bac1b974..d48c646c0 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -192,6 +192,7 @@ void pack_xilinx_simd(Module *module, const std::vector<Cell*> &selected_cells) SigSpec Y = lane->getPort("\\Y"); A.extend_u0(24, lane->getParam("\\A_SIGNED").as_bool()); B.extend_u0(24, lane->getParam("\\B_SIGNED").as_bool()); + C.append(A); AB.append(B); if (GetSize(Y) < 25) Y.append(module->addWire(NEW_ID, 25-GetSize(Y))); |