diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 11:46:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 11:46:38 -0700 |
| commit | fe5a1324c953cee51774228723e73a2ecac9a45b (patch) | |
| tree | 05796d367056eb409e6b2cde1e2a495d493f61cc /passes/pmgen/xilinx_dsp.cc | |
| parent | 447a31e75d7bd77c0108eb0c76b9749340b10db4 (diff) | |
| download | yosys-fe5a1324c953cee51774228723e73a2ecac9a45b.tar.gz yosys-fe5a1324c953cee51774228723e73a2ecac9a45b.tar.bz2 yosys-fe5a1324c953cee51774228723e73a2ecac9a45b.zip | |
Do not make ff[MP]mux semioptional, use sigmap
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index a497d0a48..6e82ffac3 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -121,7 +121,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) cell->setPort("\\CEM", State::S1); SigSpec D = st.ffM->getPort("\\D"); SigSpec Q = st.ffM->getPort("\\Q"); - P.replace(/*pm.sigmap*/(D), Q); + P.replace(pm.sigmap(D), Q); cell->setParam("\\MREG", State::S1); pm.autoremove(st.ffM); @@ -135,7 +135,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) cell->setPort("\\CEP", State::S1); SigSpec D = st.ffP->getPort("\\D"); SigSpec Q = st.ffP->getPort("\\Q"); - P.replace(/*pm.sigmap*/(D), Q); + P.replace(pm.sigmap(D), Q); st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); cell->setParam("\\PREG", State::S1); @@ -149,6 +149,9 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) if (st.ffB) log(" ffB:%s", log_id(st.ffB)); + if (st.ffM) + log(" ffM:%s", log_id(st.ffM)); + if (st.ffP) log(" ffP:%s", log_id(st.ffP)); |