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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 10:07:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-05 10:07:56 -0700 |
| commit | 0166e02e781080f346b37dcb3ba6f9fa947ca22d (patch) | |
| tree | 4894e077d3c5dbed9484def21eed578fc4314d50 /passes/pmgen/xilinx_dsp.pmg | |
| parent | aa462da39513505a66840dca49a5f4499531d952 (diff) | |
| download | yosys-0166e02e781080f346b37dcb3ba6f9fa947ca22d.tar.gz yosys-0166e02e781080f346b37dcb3ba6f9fa947ca22d.tar.bz2 yosys-0166e02e781080f346b37dcb3ba6f9fa947ca22d.zip | |
Cleanup
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 339ac646c..ed5bd3aae 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -1,14 +1,14 @@ pattern xilinx_dsp state <SigBit> clock -state <SigSpec> sigA sigffAmux sigB sigC sigM sigP sigPused +state <SigSpec> sigA sigffAmux sigB sigC sigM sigP state <IdString> ffAmuxAB ffMmuxAB postAddAB postAddMuxAB match dsp select dsp->type.in(\DSP48E1) endmatch -code sigA sigB +code sigA sigffAmux sigB sigM sigA = port(dsp, \A); int i; for (i = GetSize(sigA)-1; i > 0; i--) @@ -26,12 +26,9 @@ code sigA sigB if (sigB[i].wire) ++i; sigB.remove(i, GetSize(sigB)-i); -endcode -code sigM SigSpec P = port(dsp, \P); // Only care about those bits that are used - int i; for (i = 0; i < GetSize(P); i++) { if (nusers(P[i]) <= 1) break; |