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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:45:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:45:25 -0700 |
| commit | 91629ee4b3aae3aa8243a659ffe1716ad5c432a2 (patch) | |
| tree | 98f0e293b418e04aadd0bcb427e8c23927357849 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 8dca8d486e945eb5883e6757f711011ed23aa5ba (diff) | |
| download | yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.tar.gz yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.tar.bz2 yosys-91629ee4b3aae3aa8243a659ffe1716ad5c432a2.zip | |
Pattern matcher to check pool of bits, not exactly
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 4b7bea308..60e972615 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -11,7 +11,7 @@ match ffA select ffA->type.in($dff, $dffe) select param(ffA, \CLK_POLARITY).as_bool() // select nusers(port(ffA, \Q)) == 2 - index <SigSpec> port(ffA, \Q).extend_u0(25, true) === port(dsp, \A).extract(0, 25) + index <SigSpec> port(ffA, \Q).to_sigbit_pool() === port(dsp, \A).remove_const().to_sigbit_pool() // DSP48E1 does not support clock inversion optional endmatch @@ -25,7 +25,7 @@ match ffB select ffB->type.in($dff, $dffe) select param(ffB, \CLK_POLARITY).as_bool() // select nusers(port(ffB, \Q)) == 2 - index <SigSpec> port(ffB, \Q).extend_u0(18, true) === port(dsp, \B) + index <SigSpec> port(ffB, \Q).to_sigbit_pool() === port(dsp, \B).remove_const().to_sigbit_pool() optional endmatch |