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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
| commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
| tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /passes/pmgen/xilinx_dsp_CREG.pmg | |
| parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes/pmgen/xilinx_dsp_CREG.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index a57043009..5cd34162e 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -63,12 +63,12 @@ code sigC sigP clock if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; - for (i = 0; i < GetSize(P); i++) { - if (nusers(P[i]) <= 1) + for (i = GetSize(P)-1; i >= 0; i--) + if (nusers(P[i]) > 1) break; - sigP.append(P[i]); - } + i++; log_assert(nusers(P.extract_end(i)) <= 1); + sigP = P.extract(0, i); } else sigP = P; |