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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 14:26:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 14:26:24 -0700 |
| commit | 1c7d721558737292a6e1c5492ac8032fcdd8e31e (patch) | |
| tree | 4b0e75cf42b4fe44db19dda6d852077d9b438002 /passes/pmgen/xilinx_srl.pmg | |
| parent | cab2bd083ed25ebe1113d5fd054df5983e5086e7 (diff) | |
| download | yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.tar.gz yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.tar.bz2 yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.zip | |
Reject if not minlen from inside pattern matcher
Diffstat (limited to 'passes/pmgen/xilinx_srl.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 69a9c7af2..3a2096653 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -2,6 +2,7 @@ pattern reduce udata <vector<Cell*>> chain longest_chain udata <pool<Cell*>> non_first_cells +udata <int> minlen code non_first_cells.clear(); @@ -38,7 +39,7 @@ code finally chain.pop_back(); log_assert(chain.empty()); - if (GetSize(longest_chain) > 1) + if (GetSize(longest_chain) >= minlen) accept; endcode |