Merge branch 'eddie/xilinx_srl' into xaig_arrival

4 files changed, 603 insertions, 3 deletions

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 8e0cbdca8..e73a7b1c9 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -30,3 +30,9 @@ PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
 
 passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
 	$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
+
+# --------------------------------------
+
+OBJS += passes/pmgen/xilinx_srl.o
+passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 0ad769dfd..4f3eec935 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -28,6 +28,7 @@ bool did_something;
 
 #include "passes/pmgen/test_pmgen_pm.h"
 #include "passes/pmgen/ice40_dsp_pm.h"
+#include "passes/pmgen/xilinx_srl_pm.h"
 #include "passes/pmgen/peepopt_pm.h"
 
 void reduce_chain(test_pmgen_pm &pm)
@@ -180,7 +181,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
 		while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
 		{
 			if (timeout++ > 10000)
-				log_error("pmgen generator is stuck: 10000 iterations an no matching module generated.\n");
+				log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n");
 
 			pm matcher(mod, mod->cells());
 
@@ -216,7 +217,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
 			run(matcher, [](){});
 		}
 
-		if (submodcnt)
+		if (submodcnt && maxsubcnt < (1 << 16))
 			maxsubcnt *= 2;
 
 		design->remove(mod);
@@ -349,13 +350,18 @@ struct TestPmgenPass : public Pass {
 		if (pattern == "ice40_dsp")
 			return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp);
 
+		if (pattern == "xilinx_srl.fixed")
+			return GENERATE_PATTERN(xilinx_srl_pm, fixed);
+		if (pattern == "xilinx_srl.variable")
+			return GENERATE_PATTERN(xilinx_srl_pm, variable);
+
 		if (pattern == "peepopt-muldiv")
 			return GENERATE_PATTERN(peepopt_pm, muldiv);
 
 		if (pattern == "peepopt-shiftmul")
 			return GENERATE_PATTERN(peepopt_pm, shiftmul);
 
-		log_cmd_error("Unkown pattern: %s\n", pattern.c_str());
+		log_cmd_error("Unknown pattern: %s\n", pattern.c_str());
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
new file mode 100644
index 000000000..87fcaa15a
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.cc
@@ -0,0 +1,262 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *            (C) 2019  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// for peepopt_pm
+bool did_something;
+
+#include "passes/pmgen/xilinx_srl_pm.h"
+#include "passes/pmgen/peepopt_pm.h"
+
+void run_fixed(xilinx_srl_pm &pm)
+{
+	auto &st = pm.st_fixed;
+	auto &ud = pm.ud_fixed;
+	log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
+
+	SigSpec initval;
+	for (auto cell : ud.longest_chain) {
+		log_debug("    %s\n", log_id(cell));
+		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
+			SigBit Q = cell->getPort(ID(Q));
+			log_assert(Q.wire);
+			auto it = Q.wire->attributes.find(ID(init));
+			if (it != Q.wire->attributes.end()) {
+				auto &i = it->second[Q.offset];
+				initval.append(i);
+				i = State::Sx;
+			}
+			else
+				initval.append(State::Sx);
+		}
+		else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
+			if (cell->parameters.at(ID(INIT), State::S0).as_bool())
+				initval.append(State::S1);
+			else
+				initval.append(State::S0);
+		}
+		else
+			log_abort();
+		pm.autoremove(cell);
+	}
+
+	auto first_cell = ud.longest_chain.back();
+	auto last_cell = ud.longest_chain.front();
+	Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
+	pm.module->swap_names(c, first_cell);
+
+	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
+		c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
+		c->setParam(ID(INIT), initval.as_const());
+		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			c->setParam(ID(CLKPOL), 1);
+		else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+			c->setParam(ID(CLKPOL), 0);
+		else if (first_cell->type.in(ID(FDRE))) {
+			if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
+				c->setParam(ID(CLKPOL), 1);
+			else
+				c->setParam(ID(CLKPOL), 0);
+		}
+		else
+			log_abort();
+		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+			c->setParam(ID(ENPOL), 1);
+		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+			c->setParam(ID(ENPOL), 0);
+		else
+			c->setParam(ID(ENPOL), 2);
+
+		c->setPort(ID(C), first_cell->getPort(ID(C)));
+		c->setPort(ID(D), first_cell->getPort(ID(D)));
+		c->setPort(ID(Q), last_cell->getPort(ID(Q)));
+		c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+			c->setPort(ID(E), State::S1);
+		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			c->setPort(ID(E), first_cell->getPort(ID(E)));
+		else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
+			c->setPort(ID(E), first_cell->getPort(ID(CE)));
+		else
+			log_abort();
+	}
+	else
+		log_abort();
+
+	log("    -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
+void run_variable(xilinx_srl_pm &pm)
+{
+	auto &st = pm.st_variable;
+	auto &ud = pm.ud_variable;
+
+	log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
+
+	SigSpec initval;
+	for (const auto &i : ud.chain) {
+		auto cell = i.first;
+		auto slice = i.second;
+		log_debug("    %s\n", log_id(cell));
+		if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+			SigBit Q = cell->getPort(ID(Q))[slice];
+			log_assert(Q.wire);
+			auto it = Q.wire->attributes.find(ID(init));
+			if (it != Q.wire->attributes.end()) {
+				auto &i = it->second[Q.offset];
+				initval.append(i);
+				i = State::Sx;
+			}
+			else
+				initval.append(State::Sx);
+		}
+		else
+			log_abort();
+	}
+	pm.autoremove(st.shiftx);
+
+	auto first_cell = ud.chain.back().first;
+	auto first_slice = ud.chain.back().second;
+
+	Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
+	pm.module->swap_names(c, first_cell);
+
+	if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+		c->setParam(ID(DEPTH), GetSize(ud.chain));
+		c->setParam(ID(INIT), initval.as_const());
+		Const clkpol, enpol;
+		if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			clkpol = 1;
+		else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
+			clkpol = 0;
+		else if (first_cell->type.in(ID($dff), ID($dffe)))
+			clkpol = first_cell->getParam(ID(CLK_POLARITY));
+		else
+			log_abort();
+		if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+			enpol = 1;
+		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+			enpol = 0;
+		else if (first_cell->type.in(ID($dffe)))
+			enpol = first_cell->getParam(ID(EN_POLARITY));
+		else
+			enpol = 2;
+		c->setParam(ID(CLKPOL), clkpol);
+		c->setParam(ID(ENPOL), enpol);
+
+		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			c->setPort(ID(C), first_cell->getPort(ID(C)));
+		else if (first_cell->type.in(ID($dff), ID($dffe)))
+			c->setPort(ID(C), first_cell->getPort(ID(CLK)));
+		else
+			log_abort();
+		c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
+		c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
+		c->setPort(ID(L), st.shiftx->getPort(ID(B)));
+		if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
+			c->setPort(ID(E), State::S1);
+		else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			c->setPort(ID(E), first_cell->getPort(ID(E)));
+		else if (first_cell->type.in(ID($dffe)))
+			c->setPort(ID(E), first_cell->getPort(ID(EN)));
+		else
+			log_abort();
+	}
+	else
+		log_abort();
+
+	log("    -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
+struct XilinxSrlPass : public Pass {
+	XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    xilinx_srl [options] [selection]\n");
+		log("\n");
+		log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n");
+		log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n");
+		log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n");
+		log("enable, and enable polarity (where relevant).\n");
+		log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
+		log("\n");
+		log("    -minlen N\n");
+		log("        min length of shift register (default = 3)\n");
+		log("\n");
+		log("    -fixed\n");
+		log("        infer fixed-length shift registers.\n");
+		log("\n");
+		log("    -variable\n");
+		log("        infer variable-length shift registers (i.e. fixed-length shifts where\n");
+		log("        each element also fans-out to a $shiftx cell).\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
+
+		bool fixed = false;
+		bool variable = false;
+		int minlen = 3;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
+				minlen = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-fixed") {
+				fixed = true;
+				continue;
+			}
+			if (args[argidx] == "-variable") {
+				variable = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!fixed && !variable)
+			log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
+
+		for (auto module : design->selected_modules()) {
+			auto pm = xilinx_srl_pm(module, module->selected_cells());
+			pm.ud_fixed.minlen = minlen;
+			pm.ud_variable.minlen = minlen;
+
+			if (fixed)
+				pm.run_fixed(run_fixed);
+			if (variable)
+				pm.run_variable(run_variable);
+		}
+	}
+} XilinxSrlPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
new file mode 100644
index 000000000..45d44247a
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -0,0 +1,326 @@
+pattern fixed
+
+state <IdString> clk_port en_port
+udata <vector<Cell*>> chain longest_chain
+udata <pool<Cell*>> non_first_cells
+udata <int> minlen
+
+code
+	non_first_cells.clear();
+	subpattern(setup);
+endcode
+
+match first
+	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	select !first->has_keep_attr()
+	select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+	select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+	select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
+	filter !non_first_cells.count(first)
+generate
+	SigSpec C = module->addWire(NEW_ID);
+	SigSpec D = module->addWire(NEW_ID);
+	SigSpec Q = module->addWire(NEW_ID);
+	auto r = rng(8);
+	Cell* cell;
+	switch (r)
+	{
+	case 0:
+	case 1:
+		cell = module->addCell(NEW_ID, \FDRE);
+		cell->setPort(\C, C);
+		cell->setPort(\D, D);
+		cell->setPort(\Q, Q);
+		cell->setPort(\CE, module->addWire(NEW_ID));
+		if (r & 1)
+			cell->setPort(\R, module->addWire(NEW_ID));
+		else {
+			if (rng(2) == 0)
+				cell->setPort(\R, State::S0);
+		}
+		break;
+	case 2:
+	case 3:
+		cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
+		break;
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+		cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
+		break;
+	default: log_abort();
+	}
+endmatch
+
+code clk_port en_port
+	if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
+		clk_port = \C;
+	else log_abort();
+	if (first->type.in($_DFF_N_, $_DFF_P_))
+		en_port = IdString();
+	else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+		en_port = \E;
+	else if (first->type.in(\FDRE, \FDRE_1))
+		en_port = \CE;
+	else log_abort();
+
+	longest_chain.clear();
+	chain.push_back(first);
+	subpattern(tail);
+finally
+	chain.pop_back();
+	log_assert(chain.empty());
+	if (GetSize(longest_chain) >= minlen)
+		accept;
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern setup
+arg clk_port
+arg en_port
+
+match first
+	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	select !first->has_keep_attr()
+	select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+	select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+	select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
+endmatch
+
+code clk_port en_port
+	if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
+		clk_port = \C;
+	else log_abort();
+	if (first->type.in($_DFF_N_, $_DFF_P_))
+		en_port = IdString();
+	else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+		en_port = \E;
+	else if (first->type.in(\FDRE, \FDRE_1))
+		en_port = \CE;
+	else log_abort();
+endcode
+
+match next
+	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	select !next->has_keep_attr()
+	select !port(next, \D)[0].wire->get_bool_attribute(\keep)
+	select nusers(port(next, \Q)) == 2
+	index <IdString> next->type === first->type
+	index <SigBit> port(next, \Q) === port(first, \D)
+	filter port(next, clk_port) == port(first, clk_port)
+	filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
+endmatch
+
+code
+	non_first_cells.insert(next);
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+arg clk_port
+arg en_port
+
+match next
+	semioptional
+	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	select !next->has_keep_attr()
+	select !port(next, \D)[0].wire->get_bool_attribute(\keep)
+	select nusers(port(next, \Q)) == 2
+	index <IdString> next->type === chain.back()->type
+	index <SigBit> port(next, \Q) === port(chain.back(), \D)
+	filter port(next, clk_port) == port(first, clk_port)
+	filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+	filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
+generate
+	Cell *cell = module->addCell(NEW_ID, chain.back()->type);
+	cell->setPort(\C, chain.back()->getPort(\C));
+	cell->setPort(\D, module->addWire(NEW_ID));
+	cell->setPort(\Q, chain.back()->getPort(\D));
+	if (cell->type == \FDRE) {
+		if (rng(2) == 0)
+			cell->setPort(\R, chain.back()->connections_.at(\R, State::S0));
+		cell->setPort(\CE, chain.back()->getPort(\CE));
+	}
+	else if (cell->type.begins_with("$_DFFE_"))
+		cell->setPort(\E, chain.back()->getPort(\E));
+endmatch
+
+code
+	if (next) {
+		chain.push_back(next);
+		subpattern(tail);
+	} else {
+		if (GetSize(chain) > GetSize(longest_chain))
+			longest_chain = chain;
+	}
+finally
+	if (next)
+		chain.pop_back();
+endcode
+
+// -----------
+
+pattern variable
+
+state <IdString> clk_port en_port
+state <int> shiftx_width
+state <int> slice
+udata <int> minlen
+udata <vector<pair<Cell*,int>>> chain
+udata <pool<SigBit>> chain_bits
+
+code
+	chain_bits.clear();
+endcode
+
+match shiftx
+	select shiftx->type.in($shiftx)
+	select !shiftx->has_keep_attr()
+	select param(shiftx, \Y_WIDTH).as_int() == 1
+	filter param(shiftx, \A_WIDTH).as_int() >= minlen
+generate
+	minlen = 3;
+	module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
+endmatch
+
+code shiftx_width
+	shiftx_width = param(shiftx, \A_WIDTH).as_int();
+endcode
+
+match first
+	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
+	select !first->has_keep_attr()
+	select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
+	slice idx GetSize(port(first, \Q))
+	select nusers(port(first, \Q)[idx]) <= 2
+	index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
+	set slice idx
+generate
+	SigSpec C = module->addWire(NEW_ID);
+	auto WIDTH = rng(3)+1;
+	SigSpec D = module->addWire(NEW_ID, WIDTH);
+	SigSpec Q = module->addWire(NEW_ID, WIDTH);
+	auto r = rng(8);
+	Cell *cell = nullptr;
+	switch (r)
+	{
+	case 0:
+	case 1:
+		cell = module->addDff(NEW_ID, C, D, Q, r & 1);
+		break;
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+		//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
+		//break;
+	case 6:
+	case 7:
+		WIDTH = 1;
+		cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
+		break;
+	default: log_abort();
+	}
+	shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)];
+endmatch
+
+code clk_port en_port
+	if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+		clk_port = \C;
+	else if (first->type.in($dff, $dffe))
+		clk_port = \CLK;
+	else log_abort();
+	if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
+		en_port = IdString();
+	else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+		en_port = \E;
+	else if (first->type.in($dffe))
+		en_port = \EN;
+	else log_abort();
+
+	chain_bits.insert(port(first, \Q)[slice]);
+	chain.emplace_back(first, slice);
+	subpattern(tail);
+finally
+	if (GetSize(chain) == shiftx_width)
+		accept;
+	chain.clear();
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+arg shiftx
+arg shiftx_width
+arg slice
+arg clk_port
+arg en_port
+
+match next
+	semioptional
+	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
+	select !next->has_keep_attr()
+	select !port(next, \D)[0].wire->get_bool_attribute(\keep)
+	slice idx GetSize(port(next, \Q))
+	select nusers(port(next, \Q)[idx]) <= 3
+	index <IdString> next->type === chain.back().first->type
+	index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
+	index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
+	filter port(next, clk_port) == port(first, clk_port)
+	filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+	filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool()
+	filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool()
+	filter !chain_bits.count(port(next, \D)[idx])
+	set slice idx
+generate
+	if (GetSize(chain) < shiftx_width) {
+		auto back = chain.back().first;
+		auto slice = chain.back().second;
+		if (back->type.in($dff, $dffe)) {
+			auto WIDTH = GetSize(port(back, \D));
+			if (rng(2) == 0 && slice < WIDTH-1) {
+				auto new_slice = slice + rng(WIDTH-1-slice);
+				back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
+			}
+			else {
+				auto D = module->addWire(NEW_ID, WIDTH);
+				if (back->type == $dff)
+					module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
+				else if (back->type == $dffe)
+					module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
+				else
+					log_abort();
+			}
+		}
+		else if (back->type.begins_with("$_DFF_")) {
+			Cell *cell = module->addCell(NEW_ID, back->type);
+			cell->setPort(\C, back->getPort(\C));
+			cell->setPort(\D, module->addWire(NEW_ID));
+			cell->setPort(\Q, back->getPort(\D));
+		}
+		else
+			log_abort();
+		shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice];
+	}
+endmatch
+
+code
+	if (next) {
+		chain_bits.insert(port(next, \Q)[slice]);
+		chain.emplace_back(next, slice);
+		if (GetSize(chain) < shiftx_width)
+			subpattern(tail);
+	}
+endcode