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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:07:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:07:54 -0700 |
| commit | 70c5444b25f18760781509104f4393b3d0a05fc0 (patch) | |
| tree | df79a1ecc89e3a269d8dc213f87e6b371599b7e0 /passes/pmgen | |
| parent | ed187ef1cf118727a8964e26c36530560f3e37db (diff) | |
| download | yosys-70c5444b25f18760781509104f4393b3d0a05fc0.tar.gz yosys-70c5444b25f18760781509104f4393b3d0a05fc0.tar.bz2 yosys-70c5444b25f18760781509104f4393b3d0a05fc0.zip | |
Update doc
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index cff4c5ddb..0b7ffe64b 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -288,8 +288,8 @@ struct Ice40DspPass : public Pass { log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n"); log("\n"); log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n"); - log("({F,J,K,G}, H), output registers (O; with optional hold), and post-adder into\n"); - log("into the SB_MAC16 resource.\n"); + log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n"); + log("optional hold), and post-adder into into the SB_MAC16 resource.\n"); log("\n"); log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n"); log("input will be folded into the DSP. In this scenario only, resetting the\n"); |