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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 14:37:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 14:37:32 -0700 |
| commit | 97d11708e0104f722578b98ea70a0ba41f9e03cc (patch) | |
| tree | a67bb5531b980a3857fd0819d632787cf80ea282 /passes/pmgen | |
| parent | a09e69dd56da677f016fceeb90a68eead8a85c2f (diff) | |
| download | yosys-97d11708e0104f722578b98ea70a0ba41f9e03cc.tar.gz yosys-97d11708e0104f722578b98ea70a0ba41f9e03cc.tar.bz2 yosys-97d11708e0104f722578b98ea70a0ba41f9e03cc.zip | |
Use feedback path for MACC
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 631b93afa..9307b3d37 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -51,21 +51,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell)); SigSpec P = st.sigP; - if (st.addAB) { - log_assert(st.addAB->getParam("\\A_SIGNED").as_bool()); - log_assert(st.addAB->getParam("\\B_SIGNED").as_bool()); - log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); - - SigSpec C = st.sigC; - C.extend_u0(48, true); - cell->setPort("\\C", C); - SigSpec &opmode = cell->connections_.at("\\OPMODE"); - opmode[6] = State::S0; - opmode[5] = State::S1; - opmode[4] = State::S1; - pm.autoremove(st.addAB); - } - if (st.clock != SigBit()) { cell->setPort("\\CLK", st.clock); @@ -140,6 +125,27 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("\n"); } + if (st.addAB) { + log_assert(st.addAB->getParam("\\A_SIGNED").as_bool()); + log_assert(st.addAB->getParam("\\B_SIGNED").as_bool()); + log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); + + SigSpec C = st.sigC; + SigSpec &opmode = cell->connections_.at("\\OPMODE"); + if (cell->getParam("\\PREG").as_bool() && C == P) { + opmode[4] = State::S0; + } + else { + C.extend_u0(48, true); + cell->setPort("\\C", C); + opmode[4] = State::S1; + } + opmode[6] = State::S0; + opmode[5] = State::S1; + + pm.autoremove(st.addAB); + } + if (GetSize(P) < 48) P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); cell->setPort("\\P", P); |