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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
| commit | 052060f10906ca859d2313b86800e110bd34b79f (patch) | |
| tree | 356107e4270feb84046b984a98e0874f1436b2d9 /passes/proc/proc_arst.cc | |
| parent | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.gz yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.bz2 yosys-052060f10906ca859d2313b86800e110bd34b79f.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b69eba3f9..d069f152a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -172,7 +172,7 @@ restart_proc_arst: sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; } for (auto &action : sync->actions) { - RTLIL::SigSpec rspec = action.second; + RTLIL::SigSpec rspec = assign_map(action.second); RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) |