diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/proc/proc_arst.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
| download | yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.gz yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.bz2 yosys-4c4b6021562c598c4510831bd547edaa97d14dac.zip | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 565d86a72..63d04d351 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,7 +33,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells) { + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); |