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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-11 21:13:40 -0700 |
| commit | 88d5185596a0cc8319658463a31b20644d90dd6b (patch) | |
| tree | 106f178d42a54403218f93cae2807d6e67981599 /passes/proc/proc_arst.cc | |
| parent | 282cc77604a9a855c303869321d4179790b0b64b (diff) | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.gz yosys-88d5185596a0cc8319658463a31b20644d90dd6b.tar.bz2 yosys-88d5185596a0cc8319658463a31b20644d90dd6b.zip | |
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index d069f152a..c606deb88 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -55,7 +55,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, return check_signal(mod, cell->getPort("\\A"), ref, polarity); } - if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (!cell->getPort("\\A").as_bool()) polarity = !polarity; @@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, } } - if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { + if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) { if (cell->getPort("\\A").is_fully_const()) { if (cell->getPort("\\A").as_bool()) polarity = !polarity; |