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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-09 16:59:18 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-09 16:59:18 +0200 |
| commit | a0787c12f0acd2377fafc2836b70c31c30f7f638 (patch) | |
| tree | 19f5df3036e13bc37a32a7a5792df9c928b4bf7a /passes/proc/proc_arst.cc | |
| parent | 38e942507ea091e5fbbbcf02563919bf1e5d8f54 (diff) | |
| parent | 44bcb7a187ffa00921cb14fa50428ce272ce3b6b (diff) | |
| download | yosys-a0787c12f0acd2377fafc2836b70c31c30f7f638.tar.gz yosys-a0787c12f0acd2377fafc2836b70c31c30f7f638.tar.bz2 yosys-a0787c12f0acd2377fafc2836b70c31c30f7f638.zip | |
Merge pull request #1169 from whitequark/more-proc-cleanups
A new proc_prune pass
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b69eba3f9..d069f152a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -172,7 +172,7 @@ restart_proc_arst: sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; } for (auto &action : sync->actions) { - RTLIL::SigSpec rspec = action.second; + RTLIL::SigSpec rspec = assign_map(action.second); RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) |