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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 10:22:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-09 10:22:49 -0700 |
| commit | c91cb735620537c9f573be52cefe6267d0a9cfd8 (patch) | |
| tree | 82ffd4f014504e4b003c14fba8594f748f2beafe /passes/proc/proc_arst.cc | |
| parent | c68b9092100280dbc059526a88f9d8e2902ff6a3 (diff) | |
| parent | e95ce1f7af269447943cf1798c03b02a0c5aa1a2 (diff) | |
| download | yosys-c91cb735620537c9f573be52cefe6267d0a9cfd8.tar.gz yosys-c91cb735620537c9f573be52cefe6267d0a9cfd8.tar.bz2 yosys-c91cb735620537c9f573be52cefe6267d0a9cfd8.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b69eba3f9..d069f152a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -172,7 +172,7 @@ restart_proc_arst: sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; } for (auto &action : sync->actions) { - RTLIL::SigSpec rspec = action.second; + RTLIL::SigSpec rspec = assign_map(action.second); RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) |