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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-09 15:12:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-09 15:12:26 +0200 |
| commit | d176e613c2fea8d5ac5d9bf505b188ca13da95ef (patch) | |
| tree | 53a6e94b0cb1da5aa2b7f798ca09e22fa4464943 /passes/proc/proc_arst.cc | |
| parent | 229825e1b8936bd346829cf0ec9cf1fb3a67fc19 (diff) | |
| download | yosys-d176e613c2fea8d5ac5d9bf505b188ca13da95ef.tar.gz yosys-d176e613c2fea8d5ac5d9bf505b188ca13da95ef.tar.bz2 yosys-d176e613c2fea8d5ac5d9bf505b188ca13da95ef.zip | |
Minor fixes in handling of "init" attribute
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 27c6b3bcf..1f08ab042 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -244,6 +244,7 @@ struct ProcArstPass : public Pass { } extra_args(args, argidx, design); + pool<Wire*> delete_initattr_wires; for (auto mod : design->modules()) if (design->selected(mod)) { @@ -265,6 +266,7 @@ struct ProcArstPass : public Pass { value.extend_u0(chunk.wire->width, false); arst_sig.append(chunk); arst_val.append(value.extract(chunk.offset, chunk.width)); + delete_initattr_wires.insert(chunk.wire); } if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", @@ -281,6 +283,9 @@ struct ProcArstPass : public Pass { } } } + + for (auto wire : delete_initattr_wires) + wire->attributes.erase("\\init"); } } ProcArstPass; |