Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 14 insertions, 13 deletions

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 83554df90..1e3dd9ce7 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -27,7 +27,7 @@ extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count
 
 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
 {
-	if (sw->signal.width > 0 && sw->signal.is_fully_const())
+	if (sw->signal.size() > 0 && sw->signal.is_fully_const())
 	{
 		int found_matching_case_idx = -1;
 		for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
@@ -59,7 +59,8 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 			sw->signal = RTLIL::SigSpec();
 	}
 
-	if (sw->cases.size() == 1 && (sw->signal.width == 0 || sw->cases[0]->compare.empty()))
+	if (parent->switches.front() == sw && sw->cases.size() == 1 &&
+			(sw->signal.size() == 0 || sw->cases[0]->compare.empty()))
 	{
 		did_something = true;
 		for (auto &action : sw->cases[0]->actions)
@@ -91,7 +92,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
 {
 	for (size_t i = 0; i < cs->actions.size(); i++) {
-		if (cs->actions[i].first.width == 0) {
+		if (cs->actions[i].first.size() == 0) {
 			did_something = true;
 			cs->actions.erase(cs->actions.begin() + (i--));
 		}
@@ -114,7 +115,7 @@ static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_coun
 	bool did_something = true;
 	for (size_t i = 0; i < proc->syncs.size(); i++) {
 		for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++)
-			if (proc->syncs[i]->actions[j].first.width == 0)
+			if (proc->syncs[i]->actions[j].first.size() == 0)
 				proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--));
 		if (proc->syncs[i]->actions.size() == 0) {
 			delete proc->syncs[i];
@@ -149,23 +150,23 @@ struct ProcCleanPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
-			std::vector<std::string> delme;
-			if (!design->selected(mod_it.second))
+		for (auto mod : design->modules()) {
+			std::vector<RTLIL::IdString> delme;
+			if (!design->selected(mod))
 				continue;
-			for (auto &proc_it : mod_it.second->processes) {
-				if (!design->selected(mod_it.second, proc_it.second))
+			for (auto &proc_it : mod->processes) {
+				if (!design->selected(mod, proc_it.second))
 					continue;
-				proc_clean(mod_it.second, proc_it.second, total_count);
+				proc_clean(mod, proc_it.second, total_count);
 				if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
 						proc_it.second->root_case.actions.size() == 0) {
-					log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str());
+					log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
 					delme.push_back(proc_it.first);
 				}
 			}
 			for (auto &id : delme) {
-				delete mod_it.second->processes[id];
-				mod_it.second->processes.erase(id);
+				delete mod->processes[id];
+				mod->processes.erase(id);
 			}
 		}