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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 22:47:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 23:10:58 +0200 |
| commit | 6aa792c864444324a1b140c2b63bd860f0cc3914 (patch) | |
| tree | 07b2bf3003864337df616a21374c046ddc352c62 /passes/proc/proc_dff.cc | |
| parent | 7a608437c65e9646ed229055d61b310e7d93e37e (diff) | |
| download | yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.gz yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.bz2 yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.zip | |
Replaced more old SigChunk programming patterns
Diffstat (limited to 'passes/proc/proc_dff.cc')
| -rw-r--r-- | passes/proc/proc_dff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index a8aba903a..5982fd8e4 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -382,7 +382,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) sync_edge->signal, sync_level->signal, proc); } else - gen_dff(mod, insig, rstval.chunks()[0].data, sig, + gen_dff(mod, insig, rstval.as_const(), sig, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level ? &sync_level->signal : NULL, proc); |