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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 20:32:28 +0200 |
| commit | c094c53de83707a5bf1b268640283f1dde235873 (patch) | |
| tree | 27e480f63e0d34d8cbfcf8fcf29472c198381296 /passes/proc/proc_dff.cc | |
| parent | 8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff) | |
| download | yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.gz yosys-c094c53de83707a5bf1b268640283f1dde235873.tar.bz2 yosys-c094c53de83707a5bf1b268640283f1dde235873.zip | |
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'passes/proc/proc_dff.cc')
| -rw-r--r-- | passes/proc/proc_dff.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 8e5fbe8f4..a8aba903a 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -352,10 +352,6 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - insig.optimize(); - rstval.optimize(); - sig.optimize(); - if (rstval == sig) { rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sync_level = NULL; |