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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
commit | 052060f10906ca859d2313b86800e110bd34b79f (patch) | |
tree | 356107e4270feb84046b984a98e0874f1436b2d9 /passes/proc/proc_init.cc | |
parent | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (diff) | |
parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
download | yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.gz yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.bz2 yosys-052060f10906ca859d2313b86800e110bd34b79f.zip |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes/proc/proc_init.cc')
-rw-r--r-- | passes/proc/proc_init.cc | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index e2dc07e53..462a384b7 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -26,21 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) -{ - log_assert(rule.compare.size() == 0); - - while (1) { - RTLIL::SigSpec tmp = sig; - for (auto &it : rule.actions) - tmp.replace(it.first, it.second); - if (tmp == sig) - break; - sig = tmp; - } -} - -void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) +void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) { bool found_init = false; @@ -53,9 +39,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) for (auto &action : sync->actions) { RTLIL::SigSpec lhs = action.first; - RTLIL::SigSpec rhs = action.second; - - proc_get_const(rhs, proc->root_case); + RTLIL::SigSpec rhs = sigmap(action.second); if (!rhs.is_fully_const()) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); @@ -120,10 +104,12 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); for (auto mod : design->modules()) - if (design->selected(mod)) + if (design->selected(mod)) { + SigMap sigmap(mod); for (auto &proc_it : mod->processes) if (design->selected(mod, proc_it.second)) - proc_init(mod, proc_it.second); + proc_init(mod, sigmap, proc_it.second); + } } } ProcInitPass; |